hw/i3c/dw-i3c: Add controller resets
Adds behavior to the device reset register. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Stephen Longfield <slongfield@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-17-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
e5527d0e31495c1ebad148fd88193450c17c8c37
2 files changed
+118
hw/i3c/dw-i3c.c
+117
@@ -860,6 +860,122 @@ static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val)
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dw_i3c_update_irq(s);
861
}
862
863
+static void dw_i3c_cmd_queue_reset(DWI3C *s)
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+{
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+ fifo32_reset(&s->cmd_queue);
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+
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+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
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+ fifo32_num_free(&s->cmd_queue));
869
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
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+ CMD_BUF_EMPTY_THLD);
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+ if (fifo32_num_free(&s->cmd_queue) >= empty_threshold) {
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+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1);
873
+ dw_i3c_update_irq(s);
874
+ };
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+}
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+
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+static void dw_i3c_resp_queue_reset(DWI3C *s)
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+{
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+ fifo32_reset(&s->resp_queue);
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+
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+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR,
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+ fifo32_num_used(&s->resp_queue));
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+ /*
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+ * This interrupt will always be cleared because the threshold is a minimum
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+ * of 1 and the queue size is 0.
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+ */
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+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0);
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+ dw_i3c_update_irq(s);
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+}
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+
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+static void dw_i3c_ibi_queue_reset(DWI3C *s)
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+{
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+ fifo32_reset(&s->ibi_queue);
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+
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+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR,
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+ fifo32_num_used(&s->resp_queue));
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+ /*
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+ * This interrupt will always be cleared because the threshold is a minimum
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+ * of 1 and the queue size is 0.
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+ */
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+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0);
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+ dw_i3c_update_irq(s);
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+}
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+
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+static void dw_i3c_tx_queue_reset(DWI3C *s)
906
+{
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+ fifo32_reset(&s->tx_queue);
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+
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+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
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+ fifo32_num_free(&s->tx_queue));
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+ /* TX buf is empty, so this interrupt will always be set. */
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+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1);
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+ dw_i3c_update_irq(s);
914
+}
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+
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+static void dw_i3c_rx_queue_reset(DWI3C *s)
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+{
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+ fifo32_reset(&s->rx_queue);
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+
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+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR,
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+ fifo32_num_used(&s->resp_queue));
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+ /*
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+ * This interrupt will always be cleared because the threshold is a minimum
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+ * of 1 and the queue size is 0.
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+ */
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+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0);
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+ dw_i3c_update_irq(s);
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+}
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+
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+static void dw_i3c_reset(DeviceState *dev)
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+{
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+ DWI3C *s = DW_I3C(dev);
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+ trace_dw_i3c_reset(s->cfg.id);
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+
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+ memcpy(s->regs, dw_i3c_resets, sizeof(s->regs));
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+ /*
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+ * The user config for these may differ from our resets array, set them
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+ * manually.
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+ */
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+ ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR,
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+ s->cfg.dev_addr_table_pointer);
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+ ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH,
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+ s->cfg.dev_addr_table_depth);
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+ ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER,
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+ P_DEV_CHAR_TABLE_START_ADDR,
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+ s->cfg.dev_char_table_pointer);
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+ ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,
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+ s->cfg.dev_char_table_depth);
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+
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+ dw_i3c_cmd_queue_reset(s);
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+ dw_i3c_resp_queue_reset(s);
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+ dw_i3c_ibi_queue_reset(s);
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+ dw_i3c_tx_queue_reset(s);
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+ dw_i3c_rx_queue_reset(s);
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+}
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+
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+static void dw_i3c_reset_ctrl_w(DWI3C *s, uint32_t val)
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+{
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+ if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) {
960
+ dw_i3c_reset(DEVICE(s));
961
+ }
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+ if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) {
963
+ dw_i3c_cmd_queue_reset(s);
964
+ }
965
+ if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) {
966
+ dw_i3c_resp_queue_reset(s);
967
+ }
968
+ if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) {
969
+ dw_i3c_tx_queue_reset(s);
970
+ }
971
+ if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) {
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+ dw_i3c_rx_queue_reset(s);
973
+ }
974
+ if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) {
975
+ dw_i3c_ibi_queue_reset(s);
976
+ }
977
+}
978
+
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static uint32_t dw_i3c_pop_rx(DWI3C *s)
980
{
981
if (fifo32_is_empty(&s->rx_queue)) {
@@ -1617,6 +1733,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
1733
dw_i3c_cmd_queue_port_w(s, val32);
1734
break;
1735
case R_RESET_CTRL:
1736
+ dw_i3c_reset_ctrl_w(s, val32);
1737
break;
1738
case R_INTR_STATUS:
1739
dw_i3c_intr_status_w(s, val32);
hw/i3c/trace-events
+1
@@ -11,6 +11,7 @@ dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 "
11
dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus"
12
dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8
13
dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d"
14
+dw_i3c_reset(uint32_t deviceid) "I3C Dev[%u] reset"
15
dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO"
16
dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue"
17
dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO"