target/riscv: Introduce externally facing CSR access functions
Convert riscv_csr_[read|write]() into target_ulong angnostic CSR access functions that can be safely used from outside of target/ without knowledge of the target register size. Replace the 4 existing CSR accesses in hw/ and linux-user/. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-25-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:54 UTC
e59bd5cdb7d28a8ea0ee0b3ddabad17b296386a5
5 files changed
+27
-20
hw/riscv/riscv_hart.c
+3
-4
@@ -67,12 +67,11 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
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RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
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CPURISCVState *env = &cpu->env;
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- int ret = RISCV_EXCP_NONE;
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+ RISCVException ret = RISCV_EXCP_NONE;
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if (strcmp(cmd, "get_csr") == 0) {
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- ret = riscv_csrr(env, csrno, (target_ulong *)val);
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+ ret = riscv_csr_read_i64(env, csrno, val);
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} else if (strcmp(cmd, "set_csr") == 0) {
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- ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
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- MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
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+ ret = riscv_csr_write_i64(env, csrno, *val);
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}
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g_assert(ret == RISCV_EXCP_NONE);
linux-user/riscv/signal.c
+3
-2
@@ -90,7 +90,8 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
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__put_user(env->fpr[i], &sc->fpr[i]);
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}
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- uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
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+ uint64_t fcsr;
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+ riscv_csr_read_i64(env, CSR_FCSR, &fcsr);
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__put_user(fcsr, &sc->fcsr);
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}
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@@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
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uint32_t fcsr;
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__get_user(fcsr, &sc->fcsr);
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- riscv_csr_write(env, CSR_FCSR, fcsr);
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+ riscv_csr_write_i64(env, CSR_FCSR, fcsr);
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}
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static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
target/riscv/cpu.h
+6
-1
@@ -905,7 +905,12 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
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RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);
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uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
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-#include "target/riscv/csr.h"
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+/*
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+ * Externally facing CSR access functions, wrappers around riscv_csr*().
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+ */
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+
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+RISCVException riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val);
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+RISCVException riscv_csr_read_i64(CPURISCVState *env, int csrn, uint64_t *res);
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/*
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* The event id are encoded based on the encoding specified in the
target/riscv/csr.c
+15
@@ -5751,6 +5751,21 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
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return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, ra);
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}
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+RISCVException riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val)
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+{
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+ return riscv_csrrw(env, csrno, NULL, val,
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+ MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
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+}
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+
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+RISCVException riscv_csr_read_i64(CPURISCVState *env, int csrno, uint64_t *res)
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+{
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+ RISCVException ret;
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+ target_ulong val = 0;
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+ ret = riscv_csrr(env, csrno, &val);
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+ *res = val;
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+ return ret;
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+}
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+
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static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
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Int128 *ret_value,
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Int128 new_value,
target/riscv/csr.h
-13
@@ -26,19 +26,6 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
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target_ulong new_value,
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target_ulong write_mask);
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-static inline void riscv_csr_write(CPURISCVState *env, int csrno,
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- target_ulong val)
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-{
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- riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
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-}
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-
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-static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
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-{
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- target_ulong val = 0;
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- riscv_csrr(env, csrno, &val);
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- return val;
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-}
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-
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typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
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int csrno);
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typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,