target/arm: Factor aarch64_aa32_a57_init() out
In order to make the following commit easier to review, factor aarch64_aa32_a57_init() out of aarch64_a57_initfn() as a preliminary step. We only add a %aa32_only argument to restrict AArch64 features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-14-philmd@linaro.org>
Philippe Mathieu-Daudé committed
May 15, 2026 at 11:49 UTC
e5ab3ee28d8235f0975ba44e477fcc3915163c02
1 file changed
+24
-12
target/arm/cpu64.c
+24
-12
@@ -686,17 +686,20 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
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SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
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}
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-static void aarch64_a57_initfn(Object *obj)
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+static void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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ARMISARegisters *isar = &cpu->isar;
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+ const bool aarch64_enabled = !aa32_only;
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cpu->dtb_compatible = "arm,cortex-a57";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
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- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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+ if (aarch64_enabled) {
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+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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+ }
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -727,10 +730,12 @@ static void aarch64_a57_initfn(Object *obj)
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SET_IDREG(isar, ID_ISAR4, 0x00011142);
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SET_IDREG(isar, ID_ISAR5, 0x00011121);
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SET_IDREG(isar, ID_ISAR6, 0);
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- SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
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- SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
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- SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
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- SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
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+ if (aarch64_enabled) {
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+ SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
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+ SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
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+ SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
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+ SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
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+ }
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cpu->isar.dbgdidr = 0x3516d000;
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cpu->isar.dbgdevid = 0x01110f13;
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cpu->isar.dbgdevid1 = 0x2;
@@ -742,14 +747,21 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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/* 2048KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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- set_dczid_bs(cpu, 4); /* 64 bytes */
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- cpu->gic_num_lrs = 4;
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- cpu->gic_vpribits = 5;
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- cpu->gic_vprebits = 5;
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- cpu->gic_pribits = 5;
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+ if (aarch64_enabled) {
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+ set_dczid_bs(cpu, 4); /* 64 bytes */
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+ cpu->gic_num_lrs = 4;
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+ cpu->gic_vpribits = 5;
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+ cpu->gic_vprebits = 5;
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+ cpu->gic_pribits = 5;
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+ }
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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+static void aarch64_a57_initfn(Object *obj)
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+{
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+ aarch64_aa32_a57_init(obj, false);
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+}
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+
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static void aarch64_a53_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
@@ -886,7 +898,7 @@ static void aarch64_max_initfn(Object *obj)
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}
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if (tcg_enabled() || qtest_enabled()) {
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- aarch64_a57_initfn(obj);
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+ aarch64_aa32_a57_init(obj, false);
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}
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/* '-cpu max' for TCG: we currently do this as "A57 with extra things" */