@samitouri / QOSamiQemu / commits / e5db8fb087

target/hexagon: Add hex_interrupts support

Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com> Co-authored-by: Sid Manning <sidneym@quicinc.com> Co-authored-by: Michael Lambert <mlambert@quicinc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Brian Cain committed Jun 22, 2026 at 15:28 UTC e5db8fb0878cba7c9e78b6aec1cc06b50c63ceed
4 files changed +392
target/hexagon/cpu.c
+4
@@ -54,6 +54,9 @@ static const Property hexagon_cpu_properties[] = {
54 #ifndef CONFIG_USER_ONLY
55 DEFINE_PROP_LINK("tlb", HexagonCPU, tlb, TYPE_HEXAGON_TLB,
56 HexagonTLBState *),
57 + DEFINE_PROP_UINT32("exec-start-addr", HexagonCPU, boot_addr, 0xffffffff),
58 + DEFINE_PROP_LINK("global-regs", HexagonCPU, globalregs,
59 + TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *),
60 DEFINE_PROP_UINT32("htid", HexagonCPU, htid, 0),
61 #endif
62 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),
@@ -336,6 +339,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
339
340 env->t_sreg[HEX_SREG_HTID] = cpu->htid;
341 env->threadId = cpu->htid;
342 + env->gpr[HEX_REG_PC] = cpu->boot_addr;
343 #endif
344 env->cause_code = HEX_EVENT_NONE;
345 }
target/hexagon/cpu.h
+2
@@ -197,6 +197,8 @@ struct ArchCPU {
197 bool short_circuit;
198 #ifndef CONFIG_USER_ONLY
199 HexagonTLBState *tlb;
200 + uint32_t boot_addr;
201 + HexagonGlobalRegState *globalregs;
202 uint32_t htid;
203 #endif
204 };
target/hexagon/hex_interrupts.c new
+371
@@ -0,0 +1,371 @@
1 +/*
2 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
3 + *
4 + * SPDX-License-Identifier: GPL-2.0-or-later
5 + */
6 +
7 +#include "qemu/osdep.h"
8 +#include "qemu/log.h"
9 +#include "qemu/main-loop.h"
10 +#include "cpu.h"
11 +#include "cpu_helper.h"
12 +#include "exec/cpu-interrupt.h"
13 +#include "hex_interrupts.h"
14 +#include "macros.h"
15 +#include "sys_macros.h"
16 +#include "system/cpus.h"
17 +#include "hw/hexagon/hexagon_globalreg.h"
18 +
19 +static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num);
20 +
21 +static bool get_syscfg_gie(CPUHexagonState *env)
22 +{
23 + HexagonCPU *cpu = env_archcpu(env);
24 + uint32_t syscfg =
25 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG,
26 + env->threadId);
27 + return GET_SYSCFG_FIELD(SYSCFG_GIE, syscfg);
28 +}
29 +
30 +static bool get_ssr_ex(CPUHexagonState *env)
31 +{
32 + uint32_t ssr = env->t_sreg[HEX_SREG_SSR];
33 + return GET_SSR_FIELD(SSR_EX, ssr);
34 +}
35 +
36 +static bool get_ssr_ie(CPUHexagonState *env)
37 +{
38 + uint32_t ssr = env->t_sreg[HEX_SREG_SSR];
39 + return GET_SSR_FIELD(SSR_IE, ssr);
40 +}
41 +
42 +/* Do these together so we only have to call hexagon_modify_ssr once */
43 +static void set_ssr_ex_cause(CPUHexagonState *env, int ex, uint32_t cause)
44 +{
45 + uint32_t old, new;
46 +
47 + old = env->t_sreg[HEX_SREG_SSR];
48 + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, ex);
49 + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause);
50 + new = env->t_sreg[HEX_SREG_SSR];
51 + hexagon_modify_ssr(env, new, old);
52 +}
53 +
54 +static bool get_iad_bit(CPUHexagonState *env, int int_num)
55 +{
56 + HexagonCPU *cpu = env_archcpu(env);
57 + uint32_t ipendad =
58 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
59 + env->threadId);
60 + uint32_t iad = GET_FIELD(IPENDAD_IAD, ipendad);
61 + return extract32(iad, int_num, 1);
62 +}
63 +
64 +static void set_iad_bit(CPUHexagonState *env, int int_num, int val)
65 +{
66 + HexagonCPU *cpu = env_archcpu(env);
67 + uint32_t ipendad =
68 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
69 + env->threadId);
70 + uint32_t iad = GET_FIELD(IPENDAD_IAD, ipendad);
71 + iad = deposit32(iad, int_num, 1, val);
72 + fSET_FIELD(ipendad, IPENDAD_IAD, iad);
73 + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
74 + ipendad, env->threadId);
75 +}
76 +
77 +static uint32_t get_ipend(CPUHexagonState *env)
78 +{
79 + HexagonCPU *cpu = env_archcpu(env);
80 + uint32_t ipendad =
81 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
82 + env->threadId);
83 + return GET_FIELD(IPENDAD_IPEND, ipendad);
84 +}
85 +
86 +static inline bool get_ipend_bit(CPUHexagonState *env, int int_num)
87 +{
88 + HexagonCPU *cpu = env_archcpu(env);
89 + uint32_t ipendad =
90 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
91 + env->threadId);
92 + uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
93 + return extract32(ipend, int_num, 1);
94 +}
95 +
96 +static void clear_ipend(CPUHexagonState *env, uint32_t mask)
97 +{
98 + HexagonCPU *cpu = env_archcpu(env);
99 + uint32_t ipendad =
100 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
101 + env->threadId);
102 + uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
103 + ipend &= ~mask;
104 + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
105 + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
106 + ipendad, env->threadId);
107 +}
108 +
109 +static void set_ipend(CPUHexagonState *env, uint32_t mask)
110 +{
111 + HexagonCPU *cpu = env_archcpu(env);
112 + uint32_t ipendad =
113 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
114 + env->threadId);
115 + uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
116 + ipend |= mask;
117 + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
118 + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
119 + ipendad, env->threadId);
120 +}
121 +
122 +static void set_ipend_bit(CPUHexagonState *env, int int_num, int val)
123 +{
124 + HexagonCPU *cpu = env_archcpu(env);
125 + uint32_t ipendad =
126 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
127 + env->threadId);
128 + uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
129 + ipend = deposit32(ipend, int_num, 1, val);
130 + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
131 + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
132 + ipendad, env->threadId);
133 +}
134 +
135 +static bool get_imask_bit(CPUHexagonState *env, int int_num)
136 +{
137 + uint32_t imask = env->t_sreg[HEX_SREG_IMASK];
138 + return extract32(imask, int_num, 1);
139 +}
140 +
141 +static uint32_t get_prio(CPUHexagonState *env)
142 +{
143 + uint32_t stid = env->t_sreg[HEX_SREG_STID];
144 + return extract32(stid, reg_field_info[STID_PRIO].offset,
145 + reg_field_info[STID_PRIO].width);
146 +}
147 +
148 +static void set_elr(CPUHexagonState *env, uint32_t val)
149 +{
150 + env->t_sreg[HEX_SREG_ELR] = val;
151 +}
152 +
153 +static bool get_schedcfgen(CPUHexagonState *env)
154 +{
155 + HexagonCPU *cpu = env_archcpu(env);
156 + uint32_t schedcfg =
157 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SCHEDCFG,
158 + env->threadId);
159 + return extract32(schedcfg, reg_field_info[SCHEDCFG_EN].offset,
160 + reg_field_info[SCHEDCFG_EN].width);
161 +}
162 +
163 +static bool is_lowest_prio(CPUHexagonState *env, int int_num)
164 +{
165 + uint32_t my_prio = get_prio(env);
166 + CPUState *cs;
167 +
168 + CPU_FOREACH(cs) {
169 + CPUHexagonState *hex_env = cpu_env(cs);
170 + if (!hex_is_qualified_for_int(hex_env, int_num)) {
171 + continue;
172 + }
173 +
174 + /* Note that lower values indicate *higher* priority */
175 + if (my_prio < get_prio(hex_env)) {
176 + return false;
177 + }
178 + }
179 + return true;
180 +}
181 +
182 +static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num)
183 +{
184 + bool syscfg_gie = get_syscfg_gie(env);
185 + bool iad = get_iad_bit(env, int_num);
186 + bool ssr_ie = get_ssr_ie(env);
187 + bool ssr_ex = get_ssr_ex(env);
188 + bool imask = get_imask_bit(env, int_num);
189 +
190 + return syscfg_gie && !iad && ssr_ie && !ssr_ex && !imask;
191 +}
192 +
193 +static void clear_pending_locks(CPUHexagonState *env)
194 +{
195 + g_assert(bql_locked());
196 + if (env->k0_lock_state == HEX_LOCK_WAITING) {
197 + env->k0_lock_state = HEX_LOCK_UNLOCKED;
198 + }
199 + if (env->tlb_lock_state == HEX_LOCK_WAITING) {
200 + env->tlb_lock_state = HEX_LOCK_UNLOCKED;
201 + }
202 +}
203 +
204 +static bool should_not_exec(CPUHexagonState *env)
205 +{
206 + return (get_exe_mode(env) == HEX_EXE_MODE_WAIT);
207 +}
208 +
209 +static void restore_state(CPUHexagonState *env, bool int_accepted)
210 +{
211 + CPUState *cs = env_cpu(env);
212 + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI);
213 + if (!int_accepted && should_not_exec(env)) {
214 + cpu_interrupt(cs, CPU_INTERRUPT_HALT);
215 + }
216 +}
217 +
218 +static void hex_accept_int(CPUHexagonState *env, int int_num)
219 +{
220 + CPUState *cs = env_cpu(env);
221 + HexagonCPU *cpu = env_archcpu(env);
222 + uint32_t evb =
223 + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_EVB,
224 + env->threadId);
225 + const int exe_mode = get_exe_mode(env);
226 + const bool in_wait_mode = exe_mode == HEX_EXE_MODE_WAIT;
227 +
228 + set_ipend_bit(env, int_num, 0);
229 + set_iad_bit(env, int_num, 1);
230 + set_ssr_ex_cause(env, 1, HEX_CAUSE_INT0 | int_num);
231 + cs->exception_index = HEX_EVENT_INT0 + int_num;
232 + env->cause_code = HEX_EVENT_INT0 + int_num;
233 + clear_pending_locks(env);
234 + if (in_wait_mode) {
235 + qemu_log_mask(CPU_LOG_INT,
236 + "%s: thread " TARGET_FMT_ld " resuming, exiting WAIT mode\n",
237 + __func__, env->threadId);
238 + set_elr(env, env->wait_next_pc);
239 + clear_wait_mode(env);
240 + cs->halted = false;
241 + } else if (env->k0_lock_state == HEX_LOCK_WAITING) {
242 + g_assert_not_reached();
243 + } else {
244 + set_elr(env, env->gpr[HEX_REG_PC]);
245 + }
246 + env->gpr[HEX_REG_PC] = evb | (cs->exception_index << 2);
247 + if (get_ipend(env) == 0) {
248 + restore_state(env, true);
249 + }
250 +}
251 +
252 +
253 +bool hex_check_interrupts(CPUHexagonState *env)
254 +{
255 + CPUState *cs = env_cpu(env);
256 + bool int_handled = false;
257 + bool ssr_ex = get_ssr_ex(env);
258 + int max_ints = 32;
259 + bool schedcfgen;
260 +
261 + /* Early exit if nothing pending */
262 + if (get_ipend(env) == 0) {
263 + restore_state(env, false);
264 + return false;
265 + }
266 +
267 + BQL_LOCK_GUARD();
268 + /* Only check priorities when schedcfgen is set */
269 + schedcfgen = get_schedcfgen(env);
270 + for (int i = 0; i < max_ints; i++) {
271 + if (!get_iad_bit(env, i) && get_ipend_bit(env, i)) {
272 + bool syscfg_gie, iad, ssr_ie, imask;
273 +
274 + qemu_log_mask(CPU_LOG_INT,
275 + "%s: thread[" TARGET_FMT_ld "] "
276 + "pc = 0x" TARGET_FMT_lx
277 + " found int %d\n",
278 + __func__, env->threadId,
279 + env->gpr[HEX_REG_PC], i);
280 + if (hex_is_qualified_for_int(env, i) &&
281 + (!schedcfgen || is_lowest_prio(env, i))) {
282 + qemu_log_mask(CPU_LOG_INT,
283 + "%s: thread[" TARGET_FMT_ld "] int %d handled_\n",
284 + __func__, env->threadId, i);
285 + hex_accept_int(env, i);
286 + int_handled = true;
287 + break;
288 + }
289 + syscfg_gie = get_syscfg_gie(env);
290 + iad = get_iad_bit(env, i);
291 + ssr_ie = get_ssr_ie(env);
292 + imask = get_imask_bit(env, i);
293 +
294 + qemu_log_mask(CPU_LOG_INT,
295 + "%s: thread[" TARGET_FMT_ld "] "
296 + "int %d not handled, qualified: %d, "
297 + "schedcfg_en: %d, low prio %d\n",
298 + __func__, env->threadId, i,
299 + hex_is_qualified_for_int(env, i), schedcfgen,
300 + is_lowest_prio(env, i));
301 +
302 + qemu_log_mask(CPU_LOG_INT,
303 + "%s: thread[" TARGET_FMT_ld "] "
304 + "int %d not handled, GIE %d, iad %d, "
305 + "SSR:IE %d, SSR:EX: %d, imask bit %d\n",
306 + __func__, env->threadId, i, syscfg_gie, iad, ssr_ie,
307 + ssr_ex, imask);
308 + }
309 + }
310 +
311 + /*
312 + * If we didn't handle the interrupt and it wasn't
313 + * because we were in EX state, then we won't be able
314 + * to execute the interrupt on this CPU unless something
315 + * changes in the CPU state. Clear the interrupt_request bits
316 + * while preserving the IPEND bits, and we can re-assert the
317 + * interrupt_request bit(s) when we execute one of those instructions.
318 + */
319 + if (!int_handled && !ssr_ex) {
320 + restore_state(env, int_handled);
321 + } else if (int_handled) {
322 + assert(!cs->halted);
323 + }
324 +
325 + return int_handled;
326 +}
327 +
328 +void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type)
329 +{
330 + if (mask == 0) {
331 + return;
332 + }
333 +
334 + /*
335 + * Notify all CPUs that the interrupt has happened
336 + */
337 + BQL_LOCK_GUARD();
338 + clear_ipend(env, mask);
339 + hex_interrupt_update(env);
340 +}
341 +
342 +void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type)
343 +{
344 + g_assert(bql_locked());
345 + if (mask == 0) {
346 + return;
347 + }
348 +
349 + /*
350 + * Notify all CPUs that the interrupt has happened
351 + */
352 + set_ipend(env, mask);
353 + hex_interrupt_update(env);
354 +}
355 +
356 +void hex_interrupt_update(CPUHexagonState *env)
357 +{
358 + CPUState *cs;
359 +
360 + g_assert(bql_locked());
361 + if (get_ipend(env) != 0) {
362 + CPU_FOREACH(cs) {
363 + CPUHexagonState *hex_env = cpu_env(cs);
364 + const int exe_mode = get_exe_mode(hex_env);
365 + if (exe_mode != HEX_EXE_MODE_OFF) {
366 + cpu_interrupt(cs, CPU_INTERRUPT_SWI);
367 + cpu_resume(cs);
368 + }
369 + }
370 + }
371 +}
target/hexagon/hex_interrupts.h new
+15
@@ -0,0 +1,15 @@
1 +/*
2 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
3 + *
4 + * SPDX-License-Identifier: GPL-2.0-or-later
5 + */
6 +
7 +#ifndef HEX_INTERRUPTS_H
8 +#define HEX_INTERRUPTS_H
9 +
10 +bool hex_check_interrupts(CPUHexagonState *env);
11 +void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type);
12 +void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type);
13 +void hex_interrupt_update(CPUHexagonState *env);
14 +
15 +#endif