78
return G_SOURCE_REMOVE;
79
}
80
81
+ /* Don't pop the FIFO if transmit is disabled. */
82
+ if (!SIFIVE_UART_TXEN(s->txctrl)) {
83
+ return G_SOURCE_REMOVE;
84
+ }
85
+
86
/* Don't pop the FIFO in case the write fails */
87
characters = fifo8_peek_bufptr(&s->tx_fifo,
88
fifo8_num_used(&s->tx_fifo), &numptr);
111
return G_SOURCE_REMOVE;
112
}
113
109
-static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf,
110
- int size)
114
+static void sifive_uart_trigger_tx_fifo(SiFiveUARTState *s)
115
{
116
uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
117
118
+ if (!timer_pending(s->fifo_trigger_handle)) {
119
+ timer_mod(s->fifo_trigger_handle, current_time +
120
+ TX_INTERRUPT_TRIGGER_DELAY_NS);
121
+ }
122
+}
123
+
124
+static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf,
125
+ int size)
126
+{
127
if (size > fifo8_num_free(&s->tx_fifo)) {
128
size = fifo8_num_free(&s->tx_fifo);
129
qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow.\n");
137
s->txfifo |= SIFIVE_UART_TXFIFO_FULL;
138
}
139
127
- if (!timer_pending(s->fifo_trigger_handle)) {
128
- timer_mod(s->fifo_trigger_handle, current_time +
129
- TX_INTERRUPT_TRIGGER_DELAY_NS);
130
- }
140
+ sifive_uart_trigger_tx_fifo(s);
141
}
142
143
static uint64_t
194
return;
195
case SIFIVE_UART_TXCTRL:
196
s->txctrl = val64;
197
+ if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) {
198
+ sifive_uart_trigger_tx_fifo(s);
199
+ }
200
return;
201
case SIFIVE_UART_RXCTRL:
202
s->rxctrl = val64;
244
{
245
SiFiveUARTState *s = opaque;
246
234
- return s->rx_fifo_len < sizeof(s->rx_fifo);
247
+ return SIFIVE_UART_RXEN(s->rxctrl) && (s->rx_fifo_len < sizeof(s->rx_fifo));
248
}
249
250
static void sifive_uart_event(void *opaque, QEMUChrEvent event)