@samitouri / QOSamiQemu / commits / e68cc2e5cd

target/riscv: enforce even register constraints for Zdinx fcvt pairs

fcvt.d.h and fcvt.h.d access a 64-bit double held in a register pair, so under Zdinx/Zhinxmin the odd-rd (fcvt.d.h) and odd-rs1 (fcvt.h.d) encodings are reserved. Add the missing REQUIRE_EVEN checks so those encodings raise an illegal-instruction exception instead of retiring. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4109 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn> Message-ID: <ea287909fd6043e0bbcdbfdcb0cc8063@wangyang25.otcaix.iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

wangyang committed Aug 13, 2026 at 18:39 UTC e68cc2e5cd28333ac76d757ed2db7d2f7635d09a

1 file changed +2

target/riscv/tcg/insn_trans/trans_rvzfh.c.inc

@@ -419,6 +419,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)

419 REQUIRE_FPU;

420 REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);

421 REQUIRE_ZDINX_OR_D(ctx);

422 + REQUIRE_EVEN(ctx, a->rd);

423

424 TCGv_i64 dest = dest_fpr(ctx, a->rd);

425 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);

@@ -453,6 +454,7 @@ static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)

454 REQUIRE_FPU;

455 REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);

456 REQUIRE_ZDINX_OR_D(ctx);

457 + REQUIRE_EVEN(ctx, a->rs1);

458

459 TCGv_i64 dest = dest_fpr(ctx, a->rd);

460 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);