target/hexagon: Add support for loadw_phys
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jun 22, 2026 at 15:28 UTC
e6f692e6278789a6a1e7235ac7d29bb8e1e9bba4
3 files changed
+7
target/hexagon/hex_common.py
+3
@@ -264,6 +264,9 @@ def need_slot(tag):
264
and "A_CVI_GATHER" not in attribdict[tag]
265
and ("A_STORE" in attribdict[tag]
266
or "A_LOAD" in attribdict[tag])
267
+ and tag != "L4_loadw_phys"
268
+ and tag != "L6_memcpy"
269
+ and tag != "Y6_dmlink"
270
):
271
return 1
272
else:
target/hexagon/imported/encode_pp.def
+1
@@ -384,6 +384,7 @@ DEF_ENC32(L4_return_fnew_pnt, ICLASS_LD" 011 0 000 sssss PP1010vv ---ddddd")
384
385
/** Load Acquire Store Release Encoding **/
386
387
+DEF_ENC32(L4_loadw_phys, ICLASS_LD" 001 0 000 sssss PP1ttttt -00ddddd")
388
DEF_ENC32(L2_loadw_locked, ICLASS_LD" 001 0 000 sssss PP000--- 000ddddd")
389
DEF_ENC32(L4_loadd_locked, ICLASS_LD" 001 0 000 sssss PP010--- 000ddddd")
390
target/hexagon/imported/ldst.idef
+3
@@ -203,6 +203,9 @@ Q6INSN(S2_storew_locked,"memw_locked(Rs32,Pd4)=Rt32", ATTRIBS(A_REGWRSIZE_4B,A_M
203
Q6INSN(L4_loadd_locked,"Rdd32=memd_locked(Rs32)", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_LOAD,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK), "Load double with lock",
204
{ fEA_REG(RsV); fLOAD_LOCKED(1,8,u,EA,RddV) })
205
206
+Q6INSN(L4_loadw_phys,"Rd32=memw_phys(Rs32,Rt32)", ATTRIBS(A_REGWRSIZE_4B,A_PRIV,A_RESTRICT_SLOT0ONLY,A_NOTE_PRIV,A_MEMSIZE_4B,A_LOAD,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), "Load word from physical address",
207
+{ fLOAD_PHYS(1,4,u,RsV,RtV,RdV); })
208
+
209
Q6INSN(S4_stored_locked,"memd_locked(Rs32,Pd4)=Rtt32", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_LATEPRED,A_NOTE_LATEPRED), "Store word with lock",
210
{ fEA_REG(RsV); fSTORE_LOCKED(1,8,EA,RttV,PdV) })
211