@samitouri / QOSamiQemu / commits / e80cf29479

tests/qtest: Add seed CSR zero extension test

Add a qtest that reads the seed CSR on RV64 machine with Zkr support and verifies that the upper 32 bits are clear. Signed-off-by: Ivan Efremov <nendensu@ispras.ru> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260802113130.7818-3-nendensu@ispras.ru> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Ivan Efremov committed Aug 2, 2026 at 14:31 UTC e80cf294797870b019d31dd299328aebdfaaa76c
1 file changed +26
tests/qtest/riscv-csr-test.c
+26
@@ -20,6 +20,12 @@
20 #define CSR_MVENDORID 0xf11
21 #define CSR_MISELECT 0x350
22
23 +#define CSR_SEED 0x015
24 +
25 +#define SEED_OPST_MASK (UINT64_C(0x3) << 30)
26 +#define SEED_OPST_ES16 (UINT64_C(0x2) << 30)
27 +#define SEED_OPST_DEAD (UINT64_C(0x3) << 30)
28 +
29 static void run_test_csr(void)
30 {
31 uint64_t res;
@@ -46,12 +52,32 @@ static void run_test_csr(void)
52 qtest_quit(qts);
53 }
54
55 +static void run_test_seed_csr(void)
56 +{
57 + uint64_t val = 0;
58 + uint64_t opst;
59 + QTestState *qts;
60 +
61 + qts = qtest_init("-machine virt -cpu tt-ascalon");
62 +
63 + qtest_csr_call(qts, "get_csr", 0, CSR_SEED, &val);
64 +
65 + opst = val & SEED_OPST_MASK;
66 + g_assert_true(opst == SEED_OPST_ES16 ||
67 + opst == SEED_OPST_DEAD);
68 +
69 + g_assert_cmphex(val >> 32, ==, 0);
70 +
71 + qtest_quit(qts);
72 +}
73 +
74 int main(int argc, char **argv)
75 {
76 g_test_init(&argc, &argv, NULL);
77
78 if (qtest_has_machine("virt")) {
79 qtest_add_func("/cpu/csr", run_test_csr);
80 + qtest_add_func("/cpu/csr/seed", run_test_seed_csr);
81 }
82
83 return g_test_run();