target/arm: Implement FTMOPA (widening, 2-way, FP8 to FP16)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260713230244.70174-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 11, 2026 at 20:14 UTC
e921da8b98f0be99edf973e3d623d79ac2cd3705
5 files changed
+64
target/arm/cpu-features.h
+5
@@ -1852,6 +1852,11 @@ static inline bool isar_feature_aa64_sme_tmop_f16f16(const ARMISARegisters *id)
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return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f16f16(id);
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}
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+static inline bool isar_feature_aa64_sme_tmop_f8f16(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f16(id);
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+}
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+
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
target/arm/tcg/fp8_helper.c
+43
@@ -1005,3 +1005,46 @@ void HELPER(sme_fmop4a_hb)(void *vza, void *vzn, void *vzm,
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FP8MulContext ctx = fp8_mul_start(env, 0xf);
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sme_mop4(vza, vzn, vzm, &ctx, desc, sizeof(float16), inner_fmop4a_hb);
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}
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+
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+void HELPER(sme_ftmopa_hb)(void *vza, void *vzn, void *vzm, void *vzk,
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+ CPUArchState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
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+ intptr_t oprsz = simd_maxsz(desc);
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+ intptr_t dim = oprsz >> MO_16;
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+ intptr_t index = simd_data(desc);
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+ intptr_t ctrl_base = (index * oprsz) >> 1;
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+ uint8_t *zn0 = vzn, *zn1 = vzn + sizeof(ARMVectorReg);
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+ uint16_t *za = vza, *zm = vzm;
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+ uint64_t *zk = vzk;
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+
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+ for (intptr_t row = 0; row < dim; row++) {
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+ uint16_t *za_row = za + tile_vslice_offset(row);
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+
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+ for (intptr_t col = 0; col < dim; col++) {
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+ uint16_t e2 = zm[H2(col)];
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+ uint16_t *e3 = za_row + H2(col);
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+ uint16_t e1 = 0;
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+
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+ /*
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+ * Four control bits select two elements. The two elements
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+ * may be non-contiguous, so assemble them locally into e1.
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+ * Pseudo-code has a double loop running forward, with a
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+ * test for (i < 2) to limit construction to 2 elements.
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+ * Easier to run a single loop backward, shifting extra
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+ * elements off the top of our uint16_t.
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+ */
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+ uint64_t this_ctrl = extractn(zk, ctrl_base + col * 4, 4);
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+ for (int i = 3; i >= 0; i--) {
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+ if (this_ctrl & (1 << i)) {
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+ bool e = i & 1;
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+ bool r = i & 2;
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+ uint8_t *p = (r ? zn1 : zn0) + H1(2 * row + e);
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+ e1 = (e1 << 8) | *p;
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+ }
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+ }
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+
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+ *e3 = f8dotadd_h(e1, e2, 2, *e3, &ctx);
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+ }
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+ }
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+}
target/arm/tcg/helper-fp8-defs.h
+2
@@ -47,3 +47,5 @@ DEF_HELPER_FLAGS_5(sme_fvdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
47
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DEF_HELPER_FLAGS_5(sme_fmop4a_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(sme_fmop4a_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+
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+DEF_HELPER_FLAGS_6(sme_ftmopa_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
target/arm/tcg/sme.decode
+2
@@ -1148,3 +1148,5 @@ FTMOPA_ss 1000 0000 010 ..... 000 ... .... .. 00 .. @tmop_o2
1148
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BFTMOPA_sh 1000 0001 010 ..... 000 ... .... .. 00 .. @tmop_o2
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FTMOPA_sh 1000 0001 011 ..... 000 ... .... .. 00 .. @tmop_o2
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+
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+FTMOPA_hb 1000 0000 011 ..... 000 ... .... .. 100 . @tmop_o1
target/arm/tcg/translate-sme.c
+12
@@ -2167,3 +2167,15 @@ TRANS_FEAT(BFTMOPA_sh, aa64_sme_tmop, do_tmop_fp,
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a, MO_32, FPST_ENV, gen_helper_sme_bftmopa_sh)
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TRANS_FEAT(FTMOPA_sh, aa64_sme_tmop, do_tmop_fp,
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a, MO_32, FPST_ENV, gen_helper_sme_ftmopa_sh)
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+
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+static bool do_tmop_fp8(DisasContext *s, arg_tmop *a, MemOp esz,
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+ gen_helper_gvec_4_ptr *fn)
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+{
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+ if (!fpmr_access_check(s)) {
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+ return true;
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+ }
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+ return do_tmop_fp(s, a, esz, FPST_ENV, fn);
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+}
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+
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+TRANS_FEAT(FTMOPA_hb, aa64_sme_tmop_f8f16, do_tmop_fp8,
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+ a, MO_16, gen_helper_sme_ftmopa_hb)