target/ppc: Move Condition Register access instructions to decodetree.
Move below instructions to decodetree specification : mfcr, mfocr, mtcrf, mtocrf : XFX-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-21-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Shivang Upadhyay committed
Aug 27, 2026 at 18:59 UTC
e93cec0f00169f0de8327e14faae22be9280e6ae
3 files changed
+86
-62
target/ppc/insn32.decode
+8
@@ -70,6 +70,9 @@
70
%dx_d 6:s10 16:5 0:1
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@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
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+&XFX rt fxm
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+@XFX ...... rt:5 . fxm:8 ...... ..... . &XFX
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+
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%md_sh 1:1 11:5
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%md_mb 5:1 6:5
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&MD rs ra sh mb rc
@@ -648,6 +651,11 @@ FSEL 111111 ..... ..... ..... ..... 10111 . @A
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652
### Move To/From System Register Instructions
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+MFCR 011111 ..... 0.... ....- 0000010011 - @XFX
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+MFOCR 011111 ..... 1.... ....- 0000010011 - @XFX
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+MTCRF 011111 ..... 0.... ....- 0010010000 - @XFX
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+MTOCRF 011111 ..... 1.... ....- 0010010000 - @XFX
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+
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SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
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SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
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SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
target/ppc/translate.c
-62
@@ -3131,40 +3131,6 @@ static void gen_mcrxrx(DisasContext *ctx)
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}
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#endif
3133
3134
-/* mfcr mfocrf */
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-static void gen_mfcr(DisasContext *ctx)
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-{
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- uint32_t crm, crn;
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-
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- if (likely(ctx->opcode & 0x00100000)) {
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- crm = CRM(ctx->opcode);
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- if (likely(crm && ((crm & (crm - 1)) == 0))) {
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- crn = ctz32(crm);
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- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
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- tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
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- cpu_gpr[rD(ctx->opcode)], crn * 4);
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- }
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- } else {
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- TCGv_i32 t0 = tcg_temp_new_i32();
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- tcg_gen_mov_i32(t0, cpu_crf[0]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[1]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[2]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[3]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[4]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[5]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[6]);
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- tcg_gen_shli_i32(t0, t0, 4);
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- tcg_gen_or_i32(t0, t0, cpu_crf[7]);
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- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
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- }
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-}
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-
3134
/* mfmsr */
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static void gen_mfmsr(DisasContext *ctx)
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{
@@ -3245,32 +3211,6 @@ static void gen_mftb(DisasContext *ctx)
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gen_op_mfspr(ctx);
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}
3213
3248
-/* mtcrf mtocrf*/
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-static void gen_mtcrf(DisasContext *ctx)
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-{
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- uint32_t crm, crn;
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-
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- crm = CRM(ctx->opcode);
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- if (likely((ctx->opcode & 0x00100000))) {
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- if (crm && ((crm & (crm - 1)) == 0)) {
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- TCGv_i32 temp = tcg_temp_new_i32();
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- crn = ctz32(crm);
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- tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
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- tcg_gen_shri_i32(temp, temp, crn * 4);
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- tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
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- }
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- } else {
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- TCGv_i32 temp = tcg_temp_new_i32();
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- tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
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- for (crn = 0 ; crn < 8 ; crn++) {
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- if (crm & (1 << crn)) {
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- tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
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- tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
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- }
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- }
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- }
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-}
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-
3214
/* mtmsr */
3215
#if defined(TARGET_PPC64)
3216
static void gen_mtmsrd(DisasContext *ctx)
@@ -5030,11 +4970,9 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
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GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
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GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
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GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
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-GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
4973
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
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GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
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GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
5037
-GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
4976
#if defined(TARGET_PPC64)
4977
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
4978
GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
target/ppc/translate/fixedpoint-impl.c.inc
+78
@@ -461,6 +461,84 @@ static bool trans_ADDEX(DisasContext *ctx, arg_X *a)
461
return true;
462
}
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464
+static bool trans_MTCRF(DisasContext *ctx, arg_MTCRF *a)
465
+{
466
+ TCGv_i32 temp;
467
+ uint32_t crm, crn;
468
+
469
+ crm = a->fxm;
470
+
471
+ temp = tcg_temp_new_i32();
472
+ tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]);
473
+
474
+ for (crn = 0 ; crn < 8 ; crn++) {
475
+ if (crm & (1 << crn)) {
476
+ tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
477
+ tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
478
+ }
479
+ }
480
+
481
+ return true;
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+}
483
+
484
+static bool trans_MTOCRF(DisasContext *ctx, arg_MTOCRF *a)
485
+{
486
+ uint32_t crm, crn;
487
+
488
+ crm = a->fxm;
489
+
490
+ /* Checking crm > 0 and set_bits(crm) == 1 */
491
+ if (crm && ((crm & (crm - 1)) == 0)) {
492
+ TCGv_i32 temp = tcg_temp_new_i32();
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+ crn = ctz32(crm);
494
+ tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]);
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+ tcg_gen_shri_i32(temp, temp, crn * 4);
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+ tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
497
+ }
498
+
499
+ return true;
500
+}
501
+
502
+static bool trans_MFOCR(DisasContext *ctx, arg_MFOCR *a)
503
+{
504
+ uint32_t crm, crn;
505
+
506
+ crm = a->fxm;
507
+
508
+ /* Checking crm > 0 and set_bits(crm) == 1 */
509
+ if (likely(crm && ((crm & (crm - 1)) == 0))) {
510
+ crn = ctz32(crm);
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+ tcg_gen_extu_i32_tl(cpu_gpr[a->rt], cpu_crf[7 - crn]);
512
+ tcg_gen_shli_tl(cpu_gpr[a->rt],
513
+ cpu_gpr[a->rt], crn * 4);
514
+ }
515
+
516
+ return true;
517
+}
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+
519
+static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a)
520
+{
521
+ TCGv_i32 t0 = tcg_temp_new_i32();
522
+ tcg_gen_mov_i32(t0, cpu_crf[0]);
523
+ tcg_gen_shli_i32(t0, t0, 4);
524
+ tcg_gen_or_i32(t0, t0, cpu_crf[1]);
525
+ tcg_gen_shli_i32(t0, t0, 4);
526
+ tcg_gen_or_i32(t0, t0, cpu_crf[2]);
527
+ tcg_gen_shli_i32(t0, t0, 4);
528
+ tcg_gen_or_i32(t0, t0, cpu_crf[3]);
529
+ tcg_gen_shli_i32(t0, t0, 4);
530
+ tcg_gen_or_i32(t0, t0, cpu_crf[4]);
531
+ tcg_gen_shli_i32(t0, t0, 4);
532
+ tcg_gen_or_i32(t0, t0, cpu_crf[5]);
533
+ tcg_gen_shli_i32(t0, t0, 4);
534
+ tcg_gen_or_i32(t0, t0, cpu_crf[6]);
535
+ tcg_gen_shli_i32(t0, t0, 4);
536
+ tcg_gen_or_i32(t0, t0, cpu_crf[7]);
537
+ tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t0);
538
+
539
+ return true;
540
+}
541
+
542
static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
543
bool compute_ov, bool compute_rc0)
544
{