hw/riscv: add create_fdt_socket_cpu_sifive()
This sifive_u only helper shares DT code with other boards. The idea is to reduce code repetition while keeping sifive_u characteristics in place. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260615203734.954428-14-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jun 15, 2026 at 17:37 UTC
e968e487acf082279118667f495a3f4275a59d59
3 files changed
+18
-21
hw/riscv/fdt-common.c
+11
@@ -189,3 +189,14 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts,
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is_32_bit);
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}
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}
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+
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+void
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+create_fdt_socket_cpu_sifive(void *fdt, char *clust_name,
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+ int cpu_id, int socket_id,
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+ int socket_hartid_base, uint32_t *phandle,
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+ uint32_t *intc_phandles)
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+{
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+ create_fdt_socket_cpu_internal(fdt, clust_name, NULL, cpu_id,
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+ socket_id, socket_hartid_base,
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+ phandle, intc_phandles, false, false);
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+}
hw/riscv/sifive_u.c
+3
-21
@@ -145,12 +145,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
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qemu_fdt_add_subnode(fdt, clust_name);
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for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
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- int cpu_phandle = phandle++;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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- char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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- g_autofree char *core_name = NULL;
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-
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qemu_fdt_add_subnode(fdt, nodename);
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+
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/* cpu 0 is the management hart that does not have mmu */
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if (cpu != 0) {
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if (is_32_bit) {
@@ -162,25 +159,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
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} else {
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riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename);
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}
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- qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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- qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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- qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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- qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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- qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
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-
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- intc_phandles[cpu] = phandle++;
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-
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- qemu_fdt_add_subnode(fdt, intc);
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- qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandles[cpu]);
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- qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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- qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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- qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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- core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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- qemu_fdt_add_subnode(fdt, core_name);
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- qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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+ create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0,
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+ &phandle, intc_phandles);
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- g_free(intc);
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g_free(nodename);
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}
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include/hw/riscv/fdt-common.h
+4
@@ -26,4 +26,8 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts,
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int socket_hartid_base, uint32_t *phandle,
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uint32_t *intc_phandles, bool numa_enabled,
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bool is_32_bit);
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+void create_fdt_socket_cpu_sifive(void *fdt, char *clust_name,
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+ int cpu_id, int socket_id,
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+ int socket_hartid_base, uint32_t *phandle,
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+ uint32_t *intc_phandles);
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#endif