hw/i3c/dw-i3c: Add more reset values
Adds reset values for the new registers added. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
e974c695757641b6466119529718d488c1a153fd
1 file changed
+19
-1
hw/i3c/dw-i3c.c
+19
-1
@@ -268,14 +268,32 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
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FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
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static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
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- [R_HW_CAPABILITY] = 0x000e00bf,
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+ /* Target mode is not supported, don't advertise it for now. */
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+ [R_HW_CAPABILITY] = 0x000e00b9,
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[R_QUEUE_THLD_CTRL] = 0x01000101,
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+ [R_DATA_BUFFER_THLD_CTRL] = 0x01010100,
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+ [R_SLV_EVENT_CTRL] = 0x0000000b,
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+ [R_QUEUE_STATUS_LEVEL] = 0x00000002,
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+ [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010,
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+ [R_PRESENT_STATE] = 0x00000003,
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[R_I3C_VER_ID] = 0x3130302a,
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[R_I3C_VER_TYPE] = 0x6c633033,
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[R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280,
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[R_DEV_CHAR_TABLE_POINTER] = 0x00020200,
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+ [R_SLV_CHAR_CTRL] = 0x00010000,
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[A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
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[R_SLV_MAX_LEN] = 0x00ff00ff,
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+ [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f,
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+ [R_SCL_I3C_OD_TIMING] = 0x000a0010,
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+ [R_SCL_I3C_PP_TIMING] = 0x000a000a,
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+ [R_SCL_I2C_FM_TIMING] = 0x00100010,
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+ [R_SCL_I2C_FMP_TIMING] = 0x00100010,
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+ [R_SCL_EXT_LCNT_TIMING] = 0x20202020,
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+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000,
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+ [R_BUS_FREE_TIMING] = 0x00200020,
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+ [R_BUS_IDLE_TIMING] = 0x00000020,
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+ [R_EXTENDED_CAPABILITY] = 0x00000239,
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+ [R_SLAVE_CONFIG] = 0x00000023,
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};
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static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)