target/ppc: Move lmw, stmw instructions to decodetree
Moving the following instructions to decodetree specification: lmw : D-form stmw : D-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the the correct register store/load behavior. Also, confirmed the register values are same before and after the change. Signed-off-by: Tanushree Shah <tshah@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-27-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Tanushree Shah committed
Aug 27, 2026 at 18:59 UTC
e98b7d5371228c2bf8c7e81ccd6ab448770b7656
5 files changed
+39
-43
target/ppc/helper.h
+2
-2
@@ -43,8 +43,8 @@ DEF_HELPER_1(check_tlb_flush_local, void, env)
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DEF_HELPER_1(check_tlb_flush_global, void, env)
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#endif
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-DEF_HELPER_3(lmw, void, env, tl, i32)
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-DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32)
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+DEF_HELPER_3(LMW, void, env, tl, i32)
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+DEF_HELPER_FLAGS_3(STMW, TCG_CALL_NO_WG, void, env, tl, i32)
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DEF_HELPER_4(LSW, void, env, tl, i32, i32)
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DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32)
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DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32)
target/ppc/insn32.decode
+3
@@ -354,6 +354,7 @@ LVDX 011111 ..... ..... ..... 0000010001 - @X
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LSKU 111010 ..... ..... ............. 0 11 @DD
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LCXU 111010 ..... ..... ............. 1 11 @DD
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+LMW 101110 ..... ..... ................ @D
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### Fixed-Point Atomic Load/Store Instructions
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@@ -399,6 +400,8 @@ STBCIX 011111 ..... ..... ..... 1111010101 - @X
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STHBRX 011111 ..... ..... ..... 1110010110 - @X
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STWBRX 011111 ..... ..... ..... 1010010110 - @X
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+STMW 101111 ..... ..... ................ @D
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+
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### Fixed-Point Compare Instructions
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CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
target/ppc/mem_helper.c
+2
-2
@@ -73,7 +73,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb,
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return NULL;
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}
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-void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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+void helper_LMW(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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uintptr_t raddr = GETPC();
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int mmu_idx = ppc_env_mmu_index(env, false);
@@ -98,7 +98,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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}
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}
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-void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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+void helper_STMW(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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uintptr_t raddr = GETPC();
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int mmu_idx = ppc_env_mmu_index(env, false);
target/ppc/translate.c
-39
@@ -2455,43 +2455,6 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
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GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
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#endif /* TARGET_PPC64 */
2457
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-/*** Integer load and store multiple ***/
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-
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-/* lmw */
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-static void gen_lmw(DisasContext *ctx)
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-{
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- TCGv t0;
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- TCGv_i32 t1;
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-
2466
- if (ctx->le_mode) {
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- gen_align_no_le(ctx);
2468
- return;
2469
- }
2470
- gen_set_access_type(ctx, ACCESS_INT);
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- t0 = tcg_temp_new();
2472
- t1 = tcg_constant_i32(rD(ctx->opcode));
2473
- gen_addr_imm_index(ctx, t0, 0);
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- gen_helper_lmw(tcg_env, t0, t1);
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-}
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-
2477
-/* stmw */
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-static void gen_stmw(DisasContext *ctx)
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-{
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- TCGv t0;
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- TCGv_i32 t1;
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-
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- if (ctx->le_mode) {
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- gen_align_no_le(ctx);
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- return;
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- }
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- gen_set_access_type(ctx, ACCESS_INT);
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- t0 = tcg_temp_new();
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- t1 = tcg_constant_i32(rS(ctx->opcode));
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- gen_addr_imm_index(ctx, t0, 0);
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- gen_helper_stmw(tcg_env, t0, t1);
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-}
2493
-
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-
2458
#if !defined(CONFIG_USER_ONLY)
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static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
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{
@@ -4695,8 +4658,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
4659
/* handles stfdp, stxsd, stxssp */
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GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
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-GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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-GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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/* ISA v3.0 changed the extended opcode from 62 to 30 */
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GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
4663
#if defined(TARGET_PPC64)
target/ppc/translate/fixedpoint-impl.c.inc
+32
@@ -288,6 +288,38 @@ static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a)
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return true;
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}
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+/* Load/Store Multiple Word */
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+static bool do_ldst_multiple(DisasContext *ctx, arg_D *a, bool store)
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+{
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+ TCGv ea;
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+ TCGv_i32 reg;
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+
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+ REQUIRE_INSNS_FLAGS(ctx, INTEGER);
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+
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+ /* Little-endian mode is not supported for multiple word operations */
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+ if (ctx->le_mode) {
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+ gen_align_no_le(ctx);
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+ return true;
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+ }
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+
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+ gen_set_access_type(ctx, ACCESS_INT);
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+
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+ reg = tcg_constant_i32(a->rt);
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+ ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si));
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+
310
+ /* Call the appropriate helper function */
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+ if (store) {
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+ gen_helper_STMW(tcg_env, ea, reg);
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+ } else {
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+ gen_helper_LMW(tcg_env, ea, reg);
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+ }
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+
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+ return true;
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+}
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+
320
+TRANS(LMW, do_ldst_multiple, false)
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+TRANS(STMW, do_ldst_multiple, true)
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+
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/*
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* Fixed-Point Compare Instructions
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*/