hw/pci-host: Split PowerNV PHB5 code from PHB4 files
Separate Power10/11 PHB5 implementation from Power9 PHB4 code for better maintainability and clarity. This is a pure code movement with no functional changes. Signed-off-by: Jishnu Warrier <jishnuvw@linux.ibm.com> Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260608093430.2729688-1-jishnuvw@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Jishnu Warrier committed
Jun 8, 2026 at 15:04 UTC
ea87cc5e3cec916ebf3f7bd320ea585913121ad3
5 files changed
+102
-64
hw/pci-host/meson.build
+2
@@ -44,5 +44,7 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
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'pnv_phb3_pbcq.c',
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'pnv_phb4.c',
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'pnv_phb4_pec.c',
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+ 'pnv_phb5.c',
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+ 'pnv_phb5_pec.c',
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'pnv_phb.c',
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))
hw/pci-host/pnv_phb4.c
-6
@@ -1721,11 +1721,6 @@ static const TypeInfo pnv_phb4_type_info = {
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}
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};
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-static const TypeInfo pnv_phb5_type_info = {
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- .name = TYPE_PNV_PHB5,
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- .parent = TYPE_PNV_PHB4,
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- .instance_size = sizeof(PnvPHB4),
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-};
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static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v,
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const char *name,
@@ -1794,7 +1789,6 @@ static void pnv_phb4_register_types(void)
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{
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type_register_static(&pnv_phb4_root_bus_info);
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type_register_static(&pnv_phb4_type_info);
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- type_register_static(&pnv_phb5_type_info);
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type_register_static(&pnv_phb4_iommu_memory_region_info);
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}
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hw/pci-host/pnv_phb4_pec.c
-58
@@ -394,67 +394,9 @@ static const TypeInfo pnv_pec_type_info = {
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}
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};
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-/*
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- * POWER10 definitions
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- */
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-static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
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-{
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- return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
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-}
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-
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-static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
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-{
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- return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
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-}
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-
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-static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
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-{
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- /* index goes down ... */
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- return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
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-}
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-
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-/*
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- * PEC0 -> 3 stacks
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- * PEC1 -> 3 stacks
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- */
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-static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
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-
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-static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
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-{
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- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
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- static const char compat[] = "ibm,power10-pbcq";
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- static const char stk_compat[] = "ibm,power10-phb-stack";
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-
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- pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
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- pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
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- pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
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- pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
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- pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
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- pecc->compat = compat;
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- pecc->compat_size = sizeof(compat);
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- pecc->stk_compat = stk_compat;
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- pecc->stk_compat_size = sizeof(stk_compat);
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- pecc->version = PNV_PHB5_VERSION;
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- pecc->phb_type = TYPE_PNV_PHB5;
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- pecc->num_phbs = pnv_phb5_pec_num_stacks;
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-}
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-
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-static const TypeInfo pnv_phb5_pec_type_info = {
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- .name = TYPE_PNV_PHB5_PEC,
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- .parent = TYPE_PNV_PHB4_PEC,
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- .instance_size = sizeof(PnvPhb4PecState),
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- .class_init = pnv_phb5_pec_class_init,
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- .class_size = sizeof(PnvPhb4PecClass),
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- .interfaces = (const InterfaceInfo[]) {
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- { TYPE_PNV_XSCOM_INTERFACE },
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- { }
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- }
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-};
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-
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static void pnv_pec_register_types(void)
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{
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type_register_static(&pnv_pec_type_info);
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- type_register_static(&pnv_phb5_pec_type_info);
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}
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type_init(pnv_pec_register_types);
hw/pci-host/pnv_phb5.c
new
+23
@@ -0,0 +1,23 @@
1
+/*
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+ * QEMU PowerPC PowerNV (POWER10) PHB5 model
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+ *
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+ * Copyright (c) 2018-2026, IBM Corporation.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "hw/pci-host/pnv_phb4.h"
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+
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+static const TypeInfo pnv_phb5_type_info = {
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+ .name = TYPE_PNV_PHB5,
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+ .parent = TYPE_PNV_PHB4,
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+ .instance_size = sizeof(PnvPHB4),
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+};
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+
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+static void pnv_phb5_register_types(void)
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+{
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+ type_register_static(&pnv_phb5_type_info);
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+}
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+
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+type_init(pnv_phb5_register_types);
hw/pci-host/pnv_phb5_pec.c
new
+77
@@ -0,0 +1,77 @@
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+/*
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+ * QEMU PowerPC PowerNV (POWER10) PHB5 PEC model
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+ *
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+ * Copyright (c) 2018-2026, IBM Corporation.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "hw/pci-host/pnv_phb4.h"
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+#include "hw/ppc/pnv_xscom.h"
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+
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+#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL
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+
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+/*
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+ * POWER10 definitions
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+ */
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+static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
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+{
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+ return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
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+}
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+
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+static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
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+{
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+ return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
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+}
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+
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+static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
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+{
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+ /* index goes down ... */
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+ return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
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+}
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+
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+/*
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+ * PEC0 -> 3 stacks
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+ * PEC1 -> 3 stacks
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+ */
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+static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
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+
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+static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
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+{
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+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
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+ static const char compat[] = "ibm,power10-pbcq";
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+ static const char stk_compat[] = "ibm,power10-phb-stack";
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+
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+ pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
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+ pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
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+ pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
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+ pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
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+ pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
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+ pecc->compat = compat;
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+ pecc->compat_size = sizeof(compat);
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+ pecc->stk_compat = stk_compat;
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+ pecc->stk_compat_size = sizeof(stk_compat);
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+ pecc->version = PNV_PHB5_VERSION;
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+ pecc->phb_type = TYPE_PNV_PHB5;
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+ pecc->num_phbs = pnv_phb5_pec_num_stacks;
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+}
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+
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+static const TypeInfo pnv_phb5_pec_type_info = {
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+ .name = TYPE_PNV_PHB5_PEC,
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+ .parent = TYPE_PNV_PHB4_PEC,
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+ .instance_size = sizeof(PnvPhb4PecState),
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+ .class_init = pnv_phb5_pec_class_init,
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+ .class_size = sizeof(PnvPhb4PecClass),
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+ .interfaces = (const InterfaceInfo[]) {
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+ { TYPE_PNV_XSCOM_INTERFACE },
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+ { }
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+ }
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+};
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+
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+static void pnv_phb5_pec_register_types(void)
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+{
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+ type_register_static(&pnv_phb5_pec_type_info);
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+}
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+
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+type_init(pnv_phb5_pec_register_types);