@samitouri / QOSamiQemu / commits / ea8e5d3c50

target/riscv: Fix sstatus update in rv128

The sstatus register assignment was performed before the write mask was fully constructed, leading to an incomplete update of sstatus fields on the experimental rv128 target. Move the sstatus write after the mask completion so the full write mask is applied correctly. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chao Liu <chao.liu@processmission.com> Message-ID: <20260819105655.33391-2-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Frédéric Pétrot committed Aug 19, 2026 at 12:56 UTC ea8e5d3c504d38a6eb82a338dc48b9ba7b072153

1 file changed +2 -2

target/riscv/tcg/csr.c

+2 -2

@@ -3998,7 +3998,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,

3998 Int128 *val)

3999 {

4000 uint64_t mask = sstatus_v1_10_mask;

4001 - uint64_t sstatus = env->mstatus & mask;

4001 + uint64_t sstatus;

4002 if (env->xl != MXL_RV32 || env->debugger) {

4003 mask |= SSTATUS64_UXL;

4004 }

@@ -4009,7 +4009,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,

4009 if (env_archcpu(env)->cfg.ext_zicfilp) {

4010 mask |= SSTATUS_SPELP;

4011 }

4012 -

4012 + sstatus = env->mstatus & mask;

4013 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));

4014 return RISCV_EXCP_NONE;

4015 }