target/arm: Implement SVE floating-point convert (top, predicated, zeroing)
This includes FCVTXNT, BFCVTNT, FCVTNT, FCVTLT. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
eaa5a1a184fb69ac08dacfd9a4f6decac22d9112
2 files changed
+20
target/arm/tcg/sve.decode
+7
@@ -1941,6 +1941,13 @@ FCVTLT_hs_m 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
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FCVTNT_ds_m 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
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FCVTLT_sd_m 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTXNT_ds_z 01100100 00 0000 10 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTNT_sh_z 01100100 10 0000 00 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTNT_ds_z 01100100 11 0000 10 101 ... ..... ..... @rd_pg_rn_e0
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+BFCVTNT_z 01100100 10 0000 10 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTLT_hs_z 01100100 10 0000 01 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTLT_sd_z 01100100 11 0000 11 101 ... ..... ..... @rd_pg_rn_e0
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+
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### SVE2 floating-point convert to integer
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FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz
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target/arm/tcg/translate-sve.c
+13
@@ -8097,17 +8097,28 @@ static bool trans_RAX1(DisasContext *s, arg_RAX1 *a)
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TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64)
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+TRANS_FEAT(FCVTNT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2_fcvtnt_sh, a, 1, FPST_A64)
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TRANS_FEAT(FCVTNT_ds_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64)
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+TRANS_FEAT(FCVTNT_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2_fcvtnt_ds, a, 1, FPST_A64)
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TRANS_FEAT(BFCVTNT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_bfcvtnt, a, 0,
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s->fpcr_ah ? FPST_AH : FPST_A64)
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+TRANS_FEAT(BFCVTNT_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_bfcvtnt, a, 1,
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+ s->fpcr_ah ? FPST_AH : FPST_A64)
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TRANS_FEAT(FCVTLT_hs_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16)
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+TRANS_FEAT(FCVTLT_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2_fcvtlt_hs, a, 1, FPST_A64_F16)
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TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64)
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+TRANS_FEAT(FCVTLT_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2_fcvtlt_sd, a, 1, FPST_A64)
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TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a,
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FPROUNDING_ODD, 0, gen_helper_sve_fcvt_ds)
@@ -8116,6 +8127,8 @@ TRANS_FEAT(FCVTX_ds_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a,
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FPROUNDING_ODD, 0, gen_helper_sve2_fcvtnt_ds)
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+TRANS_FEAT(FCVTXNT_ds_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_ODD, 1, gen_helper_sve2_fcvtnt_ds)
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static gen_helper_gvec_3_ptr * const flogb_fns[] = {
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NULL, gen_helper_flogb_h,