target/riscv: use SXL instead of MXL for read_sstatus
According to the RISC-V spec, a 64-bit system can have M-mode in 64-bit with S-mode being 32-bit (SXL bits or mstatus[35:34] being 1). In this case, read_sstatus should use SXL. QEMU doesn't allow changing the SXL bits in mstatus in M-mode. This was because of the missing MSTATUS64_SXL mask in write_mstatus. Now, both the SXL field in mstatus can be safely modified in M-mode and read_sstatus correctly uses SXL not MXL. Fixes: b550f89457 ("target/riscv: Compute mstatus.sd on demand") Signed-off-by: Abhigyan Kumar <314abh@gmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260723142254.1683113-1-314abh@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Abhigyan Kumar committed
Jul 23, 2026 at 19:52 UTC
ebef6685a1a29b0b106b6ff3931ffc22c489e0ae
1 file changed
+7
-2
target/riscv/tcg/csr.c
+7
-2
@@ -2067,6 +2067,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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}
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if (xl != MXL_RV32 || env->debugger) {
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+ if ((val & MSTATUS64_SXL) != 0) {
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+ mask |= MSTATUS64_SXL;
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+ val = riscv_write_uxl(env, val, MSTATUS64_SXL);
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+ }
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+
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if ((val & MSTATUS64_UXL) != 0) {
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mask |= MSTATUS64_UXL;
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val = riscv_write_uxl(env, val, MSTATUS64_UXL);
@@ -4014,8 +4019,8 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
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if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
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mask |= SSTATUS_SDT;
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}
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- /* TODO: Use SXL not MXL. */
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- *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
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+
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+ *val = add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask);
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return RISCV_EXCP_NONE;
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}
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