hw/i3c/dw-i3c: Treat more registers as read-as-zero
RESET_CTRL and INTR_FORCE are write-only. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
ec449d0dcec26e24f37525f526d62803c9845b38
1 file changed
+3
hw/i3c/dw-i3c.c
+3
@@ -342,7 +342,10 @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
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uint64_t value;
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switch (addr) {
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+ /* RAZ */
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case R_COMMAND_QUEUE_PORT:
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+ case R_RESET_CTRL:
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+ case R_INTR_FORCE:
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value = 0;
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break;
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default: