target/arm: Set fgt in cpregs for FGWTE3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260806172709.333300-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 6, 2026 at 10:27 UTC
ee437322f4a06c07ab68e5e68d8e8fc699399a9d
2 files changed
+29
-25
target/arm/cpregs-gcs.c
+3
-2
@@ -97,7 +97,7 @@ static const ARMCPRegInfo gcs_reginfo[] = {
97
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[2]) },
98
{ .name = "GCSCR_EL3", .state = ARM_CP_STATE_AA64,
99
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 5, .opc2 = 0,
100
- .access = PL3_RW,
100
+ .access = PL3_RW, .fgt = FGT_GCSCR_EL3,
101
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[3]) },
102
103
{ .name = "GCSPR_EL0", .state = ARM_CP_STATE_AA64,
@@ -119,7 +119,8 @@ static const ARMCPRegInfo gcs_reginfo[] = {
119
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[2]) },
120
{ .name = "GCSPR_EL3", .state = ARM_CP_STATE_AA64,
121
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 5, .opc2 = 1,
122
- .access = PL3_RW, .writefn = gcspr_write,
122
+ .access = PL3_RW, .fgt = FGT_GCSPR_EL3,
123
+ .writefn = gcspr_write,
124
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[2]) },
125
126
{ .name = "GCSPUSHM", .state = ARM_CP_STATE_AA64,
target/arm/helper.c
+26
-23
@@ -1056,7 +1056,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
1056
.resetvalue = 0 },
1057
{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1058
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1059
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1059
+ .access = PL3_RW, .fgt = FGT_MAIR_EL3,
1060
+ .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1061
.resetvalue = 0 },
1062
/*
1063
* For non-long-descriptor page tables these are PRRR and NMRR;
@@ -3728,7 +3729,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
3729
.type = ARM_CP_IO,
3730
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3731
.resetvalue = 0,
3731
- .access = PL3_RW,
3732
+ .access = PL3_RW, .fgt = FGT_MDCR_EL3,
3733
.writefn = mdcr_el3_write,
3734
.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3735
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
@@ -4498,11 +4499,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
4499
.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
4500
{ .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
4501
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
4501
- .access = PL3_RW, .resetvalue = 0,
4502
+ .access = PL3_RW, .fgt = FGT_TTBR0_EL3,
4503
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
4504
{ .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
4505
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
4505
- .access = PL3_RW,
4506
+ .access = PL3_RW, .fgt = FGT_TCR_EL3,
4507
/* no .writefn needed as this can't cause an ASID change */
4508
.resetvalue = 0,
4509
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
@@ -4524,7 +4525,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
4525
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
4526
{ .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
4527
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
4527
- .access = PL3_RW, .writefn = vbar_write,
4528
+ .access = PL3_RW, .fgt = FGT_VBAR_EL3, .writefn = vbar_write,
4529
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
4530
.resetvalue = 0 },
4531
{ .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
@@ -4533,20 +4534,20 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
4534
.fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
4535
{ .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
4536
.opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
4536
- .access = PL3_RW, .resetvalue = 0,
4537
+ .access = PL3_RW, .fgt = FGT_TPIDR_EL3,
4538
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
4539
{ .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
4540
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
4540
- .access = PL3_RW, .type = ARM_CP_CONST,
4541
- .resetvalue = 0 },
4541
+ .access = PL3_RW, .fgt = FGT_AMAIR_EL3,
4542
+ .type = ARM_CP_CONST, .resetvalue = 0 },
4543
{ .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
4544
.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
4544
- .access = PL3_RW, .type = ARM_CP_CONST,
4545
- .resetvalue = 0 },
4545
+ .access = PL3_RW, .fgt = FGT_AFSR0_EL3,
4546
+ .type = ARM_CP_CONST, .resetvalue = 0 },
4547
{ .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
4548
.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
4548
- .access = PL3_RW, .type = ARM_CP_CONST,
4549
- .resetvalue = 0 },
4549
+ .access = PL3_RW, .fgt = FGT_AFSR1_EL3,
4550
+ .type = ARM_CP_CONST, .resetvalue = 0 },
4551
};
4552
4553
#ifndef CONFIG_USER_ONLY
@@ -5114,15 +5115,17 @@ static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri,
5115
static const ARMCPRegInfo rme_reginfo[] = {
5116
{ .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
5117
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
5117
- .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset,
5118
+ .access = PL3_RW, .fgt = FGT_GPCCR_EL3,
5119
+ .writefn = gpccr_write, .resetfn = gpccr_reset,
5120
.fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) },
5121
{ .name = "GPCBW_EL3", .state = ARM_CP_STATE_AA64,
5122
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 5,
5121
- .access = PL3_RW, .writefn = gpcbw_write,
5123
+ .access = PL3_RW, .fgt = FGT_GPCBW_EL3, .writefn = gpcbw_write,
5124
.fieldoffset = offsetof(CPUARMState, cp15.gpcbw_el3) },
5125
{ .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64,
5126
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
5125
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },
5127
+ .access = PL3_RW, .fgt = FGT_GPTBR_EL3,
5128
+ .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },
5129
{ .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64,
5130
.opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5,
5131
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) },
@@ -5232,7 +5235,7 @@ static const ARMCPRegInfo mec_reginfo[] = {
5235
.fieldoffset = offsetof(CPUARMState, cp15.mecid_a1_el2) },
5236
{ .name = "MECID_RL_A_EL3", .state = ARM_CP_STATE_AA64,
5237
.opc0 = 3, .opc1 = 6, .opc2 = 1, .crn = 10, .crm = 10,
5235
- .access = PL3_RW, .accessfn = mecid_access,
5238
+ .access = PL3_RW, .accessfn = mecid_access, .fgt = FGT_MECID_RL_A_EL3,
5239
.writefn = mecid_write,
5240
.fieldoffset = offsetof(CPUARMState, cp15.mecid_rl_a_el3) },
5241
{ .name = "VMECID_P_EL2", .state = ARM_CP_STATE_AA64,
@@ -6182,7 +6185,7 @@ static const ARMCPRegInfo sctlr2_reginfo[] = {
6185
.fieldoffset = offsetof(CPUARMState, cp15.sctlr2_el[2]) },
6186
{ .name = "SCTLR2_EL3", .state = ARM_CP_STATE_AA64,
6187
.opc0 = 3, .opc1 = 6, .opc2 = 3, .crn = 1, .crm = 0,
6185
- .access = PL3_RW, .writefn = sctlr2_el3_write,
6188
+ .access = PL3_RW, .fgt = FGT_SCTLR2_EL3, .writefn = sctlr2_el3_write,
6189
.fieldoffset = offsetof(CPUARMState, cp15.sctlr2_el[3]) },
6190
};
6191
@@ -6308,7 +6311,7 @@ static const ARMCPRegInfo s1pie_reginfo[] = {
6311
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[2]) },
6312
{ .name = "PIR_EL3", .state = ARM_CP_STATE_AA64,
6313
.opc0 = 3, .opc1 = 6, .opc2 = 3, .crn = 10, .crm = 2,
6311
- .access = PL3_RW,
6314
+ .access = PL3_RW, .fgt = FGT_PIR_EL3,
6315
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[3]) },
6316
{ .name = "PIRE0_EL1", .state = ARM_CP_STATE_AA64,
6317
.opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 10, .crm = 2,
@@ -6366,7 +6369,7 @@ static const ARMCPRegInfo aie_reginfo[] = {
6369
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[2]) },
6370
{ .name = "MAIR2_EL3", .state = ARM_CP_STATE_AA64,
6371
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 1, .opc2 = 1,
6369
- .access = PL3_RW,
6372
+ .access = PL3_RW, .fgt = FGT_MAIR2_EL3,
6373
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[3]) },
6374
6375
{ .name = "AMAIR2_EL1", .state = ARM_CP_STATE_AA64,
@@ -6382,7 +6385,7 @@ static const ARMCPRegInfo aie_reginfo[] = {
6385
.type = ARM_CP_CONST, .resetvalue = 0 },
6386
{ .name = "AMAIR2_EL3", .state = ARM_CP_STATE_AA64,
6387
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 1,
6385
- .access = PL3_RW,
6388
+ .access = PL3_RW, .fgt = FGT_AMAIR2_EL3,
6389
.type = ARM_CP_CONST, .resetvalue = 0 },
6390
};
6391
@@ -7110,7 +7113,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
7113
.resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) },
7114
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
7115
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
7113
- .access = PL3_RW,
7116
+ .access = PL3_RW, .fgt = FGT_SCTLR_EL3,
7117
.raw_writefn = raw_write, .writefn = sctlr_write,
7118
.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
7119
.resetvalue = cpu->reset_sctlr },
@@ -7485,8 +7488,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
7488
.resetvalue = 0 },
7489
{ .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
7490
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
7488
- .access = PL3_RW, .type = ARM_CP_CONST,
7489
- .resetvalue = 0 },
7491
+ .access = PL3_RW, .fgt = FGT_ACTLR_EL3,
7492
+ .type = ARM_CP_CONST, .resetvalue = 0 },
7493
};
7494
define_arm_cp_regs(cpu, auxcr_reginfo);
7495
if (cpu_isar_feature(aa32_ac2, cpu)) {