target/arm: Rename SME BFCVT patterns to BFCVT_hs
The existing pattern is BFCVT (single-precision to BFloat16). In preparation for introducing more insns of the same name, append the operand sizes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
efd499ff4840eac7b7dbfc554d8c768a445eec39
4 files changed
+5
-5
target/arm/tcg/helper-sme-defs.h
+1
-1
@@ -250,7 +250,7 @@ DEF_HELPER_FLAGS_5(sme2_umlsll_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
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DEF_HELPER_FLAGS_5(sme2_usmlall_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sme2_sumlall_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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-DEF_HELPER_FLAGS_4(sme2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_4(sme2_bfcvt_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_4(sme2_bfcvtn, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_4(sme2_fcvt_n, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_4(sme2_fcvtn, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
target/arm/tcg/sme.decode
+1
-1
@@ -789,7 +789,7 @@ SUB_aaz_d 11000001 111 000010 .. 111 ...00 11 ... @az_4x4_o3
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@zz_4x2_n1 ........ ... ..... ...... .... . ..... \
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&zz_n n=1 zd=%zd_ax4 zn=%zn_ax2
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-BFCVT 11000001 011 00000 111000 ....0 ..... @zz_1x2
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+BFCVT_hs 11000001 011 00000 111000 ....0 ..... @zz_1x2
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BFCVTN 11000001 011 00000 111000 ....1 ..... @zz_1x2
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FCVT_n 11000001 001 00000 111000 ....0 ..... @zz_1x2
target/arm/tcg/sme_helper.c
+1
-1
@@ -1725,7 +1725,7 @@ DO_MLALL_IDX(sme2_sumlall_idx_s, uint32_t, int8_t, uint8_t, H4, H1, +)
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#undef DO_MLALL_IDX
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/* Convert and compress */
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-void HELPER(sme2_bfcvt)(void *vd, void *vs, float_status *fpst, uint32_t desc)
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+void HELPER(sme2_bfcvt_hs)(void *vd, void *vs, float_status *fpst, uint32_t desc)
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{
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ARMVectorReg scratch;
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size_t oprsz = simd_oprsz(desc);
target/arm/tcg/translate-sme.c
+2
-2
@@ -1448,8 +1448,8 @@ static bool do_zz_fpst(DisasContext *s, arg_zz_n *a, int data,
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return true;
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}
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-TRANS_FEAT(BFCVT, aa64_sme2, do_zz_fpst, a, 0,
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- s->fpcr_ah ? FPST_AH : FPST_A64, gen_helper_sme2_bfcvt)
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+TRANS_FEAT(BFCVT_hs, aa64_sme2, do_zz_fpst, a, 0,
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+ s->fpcr_ah ? FPST_AH : FPST_A64, gen_helper_sme2_bfcvt_hs)
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TRANS_FEAT(BFCVTN, aa64_sme2, do_zz_fpst, a, 0,
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s->fpcr_ah ? FPST_AH : FPST_A64, gen_helper_sme2_bfcvtn)
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TRANS_FEAT(FCVT_n, aa64_sme2, do_zz_fpst, a, 0,