@samitouri / QOSamiQemu / commits / f16ac872a8

target/ppc: Migrate extswsli to decodetree

Move EXTSWSLI to decodetree using the XS-form layout with a custom %xs_sh field to represent the fractured shift encoding. This replaces legacy GEN_HANDLER-based implementations with a single trans_EXTSWSLI() handler. The implementation intentionally operates directly on the destination GPR to preserve exact TCG output and avoid introducing temporary variables, matching legacy behavior. Testing: - Verified TCG equivalence with legacy implementation. Signed-off-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-2-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>

Nikhil Kumar Singh committed Aug 27, 2026 at 18:59 UTC f16ac872a8f0ebc104a6fca2a3517391f25e3c23
2 files changed +23 -28
target/ppc/insn32.decode
+8
@@ -117,6 +117,11 @@
117 &X_sa_rc rs ra rc
118 @X_sa_rc ...... rs:5 ra:5 ..... .......... rc:1 &X_sa_rc
119
120 +# XS-form with fractured shift amount
121 +%xs_sh 1:1 11:5
122 +&XS rs ra sh rc
123 +@XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=%xs_sh
124 +
125 %x_frtp 22:4 !function=times_2
126 %x_frap 17:4 !function=times_2
127 %x_frbp 12:4 !function=times_2
@@ -1301,6 +1306,9 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 ..- @XX3_at xa=%xx_xa_pair
1306 XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=%xx_xa_pair
1307 XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
1308
1309 +##Extend Sign Word and Shift Left Immediate XS-form
1310 +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS
1311 +
1312 ## Vector Division Instructions
1313
1314 VDIVSW 000100 ..... ..... ..... 00110001011 @VX
target/ppc/translate.c
+15 -28
@@ -2470,30 +2470,6 @@ static void gen_sradi1(DisasContext *ctx)
2470 gen_sradi(ctx, 1);
2471 }
2472
2473 -/* extswsli & extswsli. */
2474 -static inline void gen_extswsli(DisasContext *ctx, int n)
2475 -{
2476 - int sh = SH(ctx->opcode) + (n << 5);
2477 - TCGv dst = cpu_gpr[rA(ctx->opcode)];
2478 - TCGv src = cpu_gpr[rS(ctx->opcode)];
2479 -
2480 - tcg_gen_ext32s_tl(dst, src);
2481 - tcg_gen_shli_tl(dst, dst, sh);
2482 - if (unlikely(Rc(ctx->opcode) != 0)) {
2483 - gen_set_Rc0(ctx, dst);
2484 - }
2485 -}
2486 -
2487 -static void gen_extswsli0(DisasContext *ctx)
2488 -{
2489 - gen_extswsli(ctx, 0);
2490 -}
2491 -
2492 -static void gen_extswsli1(DisasContext *ctx)
2493 -{
2494 - gen_extswsli(ctx, 1);
2495 -}
2496 -
2473 /* srd & srd. */
2474 static void gen_srd(DisasContext *ctx)
2475 {
@@ -5750,6 +5726,21 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
5726 return true;
5727 }
5728
5729 +static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS *a)
5730 +{
5731 + REQUIRE_64BIT(ctx);
5732 + REQUIRE_INSNS_FLAGS2(ctx, ISA300);
5733 +
5734 + /* Mimic legacy behavior: operate directly on dst */
5735 + tcg_gen_ext32s_tl(cpu_gpr[a->ra], cpu_gpr[a->rs]);
5736 + tcg_gen_shli_tl(cpu_gpr[a->ra], cpu_gpr[a->ra], a->sh);
5737 +
5738 + if (unlikely(a->rc)) {
5739 + gen_set_Rc0(ctx, cpu_gpr[a->ra]);
5740 + }
5741 + return true;
5742 +}
5743 +
5744 #include "translate/fixedpoint-impl.c.inc"
5745
5746 #include "translate/fp-impl.c.inc"
@@ -5850,10 +5841,6 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
5841 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
5842 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
5843 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
5853 -GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
5854 - PPC_NONE, PPC2_ISA300),
5855 -GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
5856 - PPC_NONE, PPC2_ISA300),
5844 #endif
5845 /* handles lfdp, lxsd, lxssp */
5846 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),