target/arm: add MTX to MTEDESC and DisasContext
Add fields for MTX to DisasContext and MTEDESC. With MTE4, the fields will be needed in future patches that alter tag check, tag load and tag store behavior. Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260529-feat-mte4-v7-6-ccbd3c14eb3c@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gabriel Brookman committed
May 29, 2026 at 12:52 UTC
f1d78a5eae0d1dc984e1e9adce81b89f7ab8dc78
4 files changed
+11
target/arm/cpu.h
+1
@@ -2536,6 +2536,7 @@ FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2)
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FIELD(TBFLAG_A64, FPMR_EL, 45, 2)
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FIELD(TBFLAG_A64, MTE_STORE_ONLY, 47, 1)
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FIELD(TBFLAG_A64, MTE0_STORE_ONLY, 48, 1)
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+FIELD(TBFLAG_A64, MTX, 49, 2)
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/*
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* Helpers for using the above. Note that only the A64 accessors use
target/arm/tcg/hflags.c
+2
@@ -500,6 +500,8 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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}
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/* Cache TCMA as well as TBI. */
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DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
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+ /* Cache MTX. */
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+ DP_TBFLAG_A64(flags, MTX, mtx);
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}
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if (cpu_isar_feature(aa64_gcs, env_archcpu(env))) {
target/arm/tcg/translate-a64.c
+7
@@ -312,6 +312,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
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desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(memop));
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+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);
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desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1);
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ret = tcg_temp_new_i64();
@@ -345,6 +346,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
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desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(single_mop));
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+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);
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desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1);
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ret = tcg_temp_new_i64();
@@ -3093,6 +3095,7 @@ static void handle_sys(DisasContext *s, bool isread,
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desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
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desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);
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tcg_rt = tcg_temp_new_i64();
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gen_helper_mte_check_zva(tcg_rt, tcg_env,
@@ -4960,6 +4963,7 @@ static bool do_SET(DisasContext *s, arg_set *a, bool is_epilogue,
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desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, true);
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+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);
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/* SIZEM1 and ALIGN we leave 0 (byte write) */
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}
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/* The helper function always needs the memidx even with MTE disabled */
@@ -5014,11 +5018,13 @@ static bool do_CPY(DisasContext *s, arg_cpy *a, bool is_epilogue, CpyFn fn)
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if (s->mte_active[runpriv]) {
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rdesc = FIELD_DP32(rdesc, MTEDESC, TBI, s->tbid);
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rdesc = FIELD_DP32(rdesc, MTEDESC, TCMA, s->tcma);
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+ rdesc = FIELD_DP32(rdesc, MTEDESC, MTX, s->mtx);
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}
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if (s->mte_active[wunpriv]) {
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wdesc = FIELD_DP32(wdesc, MTEDESC, TBI, s->tbid);
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wdesc = FIELD_DP32(wdesc, MTEDESC, TCMA, s->tcma);
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wdesc = FIELD_DP32(wdesc, MTEDESC, WRITE, true);
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+ wdesc = FIELD_DP32(wdesc, MTEDESC, MTX, s->mtx);
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}
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/* The helper function needs these parts of the descriptor regardless */
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rdesc = FIELD_DP32(rdesc, MTEDESC, MIDX, rmemidx);
@@ -10809,6 +10815,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);
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dc->mte_store_only[0] = EX_TBFLAG_A64(tb_flags, MTE_STORE_ONLY);
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dc->mte_store_only[1] = EX_TBFLAG_A64(tb_flags, MTE0_STORE_ONLY);
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+ dc->mtx = EX_TBFLAG_A64(tb_flags, MTX);
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dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);
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dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
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dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);
target/arm/tcg/translate.h
+1
@@ -82,6 +82,7 @@ typedef struct DisasContext {
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uint8_t tbii; /* TBI1|TBI0 for insns */
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uint8_t tbid; /* TBI1|TBI0 for data */
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uint8_t tcma; /* TCMA1|TCMA0 for MTE */
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+ uint8_t mtx; /* MTX1|MTX0 for MTE */
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bool ns; /* Use non-secure CPREG bank on access */
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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int sve_excp_el; /* SVE exception EL or 0 if enabled */