target/riscv: Fix size of badaddr and bins
Fix these fields to 64 bits as they cannot be made smaller. Also make sure stores to these fields from TCG are 64 bits in size to avoid incorrect values on big endian hosts. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-6-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
f2287c7020f36e2f13622d9635a968d6f6fb507d
4 files changed
+8
-6
target/riscv/cpu.h
+2
-2
@@ -235,8 +235,8 @@ struct CPUArchState {
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uint8_t frm;
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float_status fp_status;
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- target_ulong badaddr;
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- target_ulong bins;
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+ uint64_t badaddr;
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+ uint64_t bins;
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target_ulong guest_phys_fault_addr;
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target/riscv/insn_trans/trans_privileged.c.inc
+1
-1
@@ -68,7 +68,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
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if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
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generate_exception(ctx, RISCV_EXCP_SEMIHOST);
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} else {
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- tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
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+ tcg_gen_st_i64(tcg_constant_i64(ebreak_addr), tcg_env,
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offsetof(CPURISCVState, badaddr));
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generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
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}
target/riscv/machine.c
+1
-1
@@ -457,7 +457,7 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINT64(env.load_res, RISCVCPU),
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VMSTATE_UINT64(env.load_val, RISCVCPU),
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VMSTATE_UINT8(env.frm, RISCVCPU),
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- VMSTATE_UINTTL(env.badaddr, RISCVCPU),
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+ VMSTATE_UINT64(env.badaddr, RISCVCPU),
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VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
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VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
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VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
target/riscv/translate.c
+4
-2
@@ -273,7 +273,7 @@ static void generate_exception(DisasContext *ctx, RISCVException excp)
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static void gen_exception_illegal(DisasContext *ctx)
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{
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- tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env,
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+ tcg_gen_st_i64(tcg_constant_i64(ctx->opcode), tcg_env,
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offsetof(CPURISCVState, bins));
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if (ctx->virt_inst_excp) {
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generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
@@ -284,7 +284,9 @@ static void gen_exception_illegal(DisasContext *ctx)
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static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
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{
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- tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr));
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+ TCGv_i64 ext = tcg_temp_new_i64();
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+ tcg_gen_extu_tl_i64(ext, target);
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+ tcg_gen_st_i64(ext, tcg_env, offsetof(CPURISCVState, badaddr));
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generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
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}
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