target/loongarch: Use sys_state in tlb_helper.c when accessing CSR registers
When accessing CSR registers in file tlb_helper.c, use sys_state rather than env. There is no function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Tested-by: Song Gao <gaosong@loongson.cn> Message-ID: <20260605082552.175336-7-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Bibo Mao committed
Jun 5, 2026 at 16:25 UTC
f298cf3aa7cd6e81ec5454a68957ed34038d16ba
1 file changed
+77
-60
target/loongarch/tcg/tlb_helper.c
+77
-60
@@ -36,16 +36,19 @@ static bool tlb_match_asid(bool global, int asid, int tlb_asid)
36
37
bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
38
{
39
+ CPUSysState *sys = env_sys(env);
40
+
41
if (tlb_ps >= 64) {
42
return false;
43
}
42
- return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2);
44
+ return BIT_ULL(tlb_ps) & (sys->CSR_PRCFG2);
45
}
46
47
static void raise_mmu_exception(CPULoongArchState *env, vaddr address,
48
MMUAccessType access_type, TLBRet tlb_error)
49
{
50
CPUState *cs = env_cpu(env);
51
+ CPUSysState *sys = env_sys(env);
52
53
switch (tlb_error) {
54
default:
@@ -62,7 +65,7 @@ static void raise_mmu_exception(CPULoongArchState *env, vaddr address,
65
} else if (access_type == MMU_INST_FETCH) {
66
cs->exception_index = EXCCODE_PIF;
67
}
65
- env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 1);
68
+ sys->CSR_TLBRERA = FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 1);
69
break;
70
case TLBRET_INVALID:
71
/* TLB match with no valid bit */
@@ -93,19 +96,19 @@ static void raise_mmu_exception(CPULoongArchState *env, vaddr address,
96
}
97
98
if (tlb_error == TLBRET_NOMATCH) {
96
- env->CSR_TLBRBADV = address;
99
+ sys->CSR_TLBRBADV = address;
100
if (is_la64(env)) {
98
- env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
101
+ sys->CSR_TLBREHI = FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI_64,
102
VPPN, extract64(address, 13, 35));
103
} else {
101
- env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
104
+ sys->CSR_TLBREHI = FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI_32,
105
VPPN, extract64(address, 13, 19));
106
}
107
} else {
105
- if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
106
- env->CSR_BADV = address;
108
+ if (!FIELD_EX64(sys->CSR_DBG, CSR_DBG, DST)) {
109
+ sys->CSR_BADV = address;
110
}
108
- env->CSR_TLBEHI = address & (TARGET_PAGE_MASK << 1);
111
+ sys->CSR_TLBEHI = address & (TARGET_PAGE_MASK << 1);
112
}
113
}
114
@@ -142,8 +145,9 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
145
LoongArchTLB *tlb;
146
uint16_t csr_asid, tlb_asid, tlb_g;
147
uint8_t tlb_e;
148
+ CPUSysState *sys = env_sys(env);
149
146
- csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
150
+ csr_asid = FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID);
151
tlb = &env->tlb[index];
152
tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
153
if (!tlb_e) {
@@ -165,25 +169,26 @@ static void sptw_prepare_context(CPULoongArchState *env, MMUContext *context)
169
{
170
uint64_t lo0, lo1, csr_vppn;
171
uint8_t csr_ps;
172
+ CPUSysState *sys = env_sys(env);
173
169
- if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
170
- csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
174
+ if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
175
+ csr_ps = FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI, PS);
176
if (is_la64(env)) {
172
- csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
177
+ csr_vppn = FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
178
} else {
174
- csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
179
+ csr_vppn = FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
180
}
176
- lo0 = env->CSR_TLBRELO0;
177
- lo1 = env->CSR_TLBRELO1;
181
+ lo0 = sys->CSR_TLBRELO0;
182
+ lo1 = sys->CSR_TLBRELO1;
183
} else {
179
- csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
184
+ csr_ps = FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, PS);
185
if (is_la64(env)) {
181
- csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
186
+ csr_vppn = FIELD_EX64(sys->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
187
} else {
183
- csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
188
+ csr_vppn = FIELD_EX64(sys->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
189
}
185
- lo0 = env->CSR_TLBELO0;
186
- lo1 = env->CSR_TLBELO1;
190
+ lo0 = sys->CSR_TLBELO0;
191
+ lo1 = sys->CSR_TLBELO1;
192
}
193
194
context->ps = csr_ps;
@@ -198,6 +203,7 @@ static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb,
203
uint64_t lo0, lo1, csr_vppn;
204
uint16_t csr_asid;
205
uint8_t csr_ps;
206
+ CPUSysState *sys = env_sys(env);
207
208
csr_vppn = context->addr >> R_TLB_MISC_VPPN_SHIFT;
209
csr_ps = context->ps;
@@ -208,7 +214,7 @@ static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb,
214
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
215
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
216
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
211
- csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
217
+ csr_asid = FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID);
218
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid);
219
220
tlb->tlb_entry0 = lo0;
@@ -241,8 +247,9 @@ static LoongArchTLB *loongarch_tlb_search_cb(CPULoongArchState *env,
247
bool tlb_g;
248
int i, compare_shift;
249
uint64_t vpn, tlb_vppn;
250
+ CPUSysState *sys = env_sys(env);
251
245
- stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
252
+ stlb_ps = FIELD_EX64(sys->CSR_STLBPS, CSR_STLBPS, PS);
253
vpn = (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1);
254
stlb_idx = vpn & 0xff; /* VA[25:15] <==> TLBIDX.index for 16KiB Page */
255
compare_shift = stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
@@ -289,9 +296,10 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
296
int csr_asid;
297
tlb_match func;
298
LoongArchTLB *tlb;
299
+ CPUSysState *sys = env_sys(env);
300
301
func = tlb_match_any;
294
- csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
302
+ csr_asid = FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID);
303
tlb = loongarch_tlb_search_cb(env, vaddr, csr_asid, func);
304
if (tlb) {
305
*index = tlb - env->tlb;
@@ -304,20 +312,21 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
312
void helper_tlbsrch(CPULoongArchState *env)
313
{
314
int index, match;
315
+ CPUSysState *sys = env_sys(env);
316
308
- if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
309
- match = loongarch_tlb_search(env, env->CSR_TLBREHI, &index);
317
+ if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
318
+ match = loongarch_tlb_search(env, sys->CSR_TLBREHI, &index);
319
} else {
311
- match = loongarch_tlb_search(env, env->CSR_TLBEHI, &index);
320
+ match = loongarch_tlb_search(env, sys->CSR_TLBEHI, &index);
321
}
322
323
if (match) {
315
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX, index);
316
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
324
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX, index);
325
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
326
return;
327
}
328
320
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
329
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
330
}
331
332
void helper_tlbrd(CPULoongArchState *env)
@@ -325,29 +334,30 @@ void helper_tlbrd(CPULoongArchState *env)
334
LoongArchTLB *tlb;
335
int index;
336
uint8_t tlb_ps, tlb_e;
337
+ CPUSysState *sys = env_sys(env);
338
329
- index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
339
+ index = FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX);
340
tlb = &env->tlb[index];
341
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
342
tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
343
344
if (!tlb_e) {
345
/* Invalid TLB entry */
336
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
337
- env->CSR_ASID = FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID, 0);
338
- env->CSR_TLBEHI = 0;
339
- env->CSR_TLBELO0 = 0;
340
- env->CSR_TLBELO1 = 0;
341
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS, 0);
346
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
347
+ sys->CSR_ASID = FIELD_DP64(sys->CSR_ASID, CSR_ASID, ASID, 0);
348
+ sys->CSR_TLBEHI = 0;
349
+ sys->CSR_TLBELO0 = 0;
350
+ sys->CSR_TLBELO1 = 0;
351
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, PS, 0);
352
} else {
353
/* Valid TLB entry */
344
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
345
- env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX,
354
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
355
+ sys->CSR_TLBIDX = FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX,
356
PS, (tlb_ps & 0x3f));
347
- env->CSR_TLBEHI = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) <<
357
+ sys->CSR_TLBEHI = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) <<
358
R_TLB_MISC_VPPN_SHIFT;
349
- env->CSR_TLBELO0 = tlb->tlb_entry0;
350
- env->CSR_TLBELO1 = tlb->tlb_entry1;
359
+ sys->CSR_TLBELO0 = tlb->tlb_entry0;
360
+ sys->CSR_TLBELO1 = tlb->tlb_entry1;
361
}
362
}
363
@@ -380,10 +390,11 @@ static void update_tlb_index(CPULoongArchState *env, MMUContext *context,
390
391
void helper_tlbwr(CPULoongArchState *env)
392
{
383
- int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
393
+ CPUSysState *sys = env_sys(env);
394
+ int index = FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX);
395
MMUContext context;
396
386
- if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
397
+ if (FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, NE)) {
398
invalidate_tlb(env, index);
399
return;
400
}
@@ -400,10 +411,11 @@ static int get_tlb_random_index(CPULoongArchState *env, vaddr addr,
411
uint16_t asid, tlb_asid, stlb_ps;
412
LoongArchTLB *tlb;
413
uint8_t tlb_e, tlb_g;
414
+ CPUSysState *sys = env_sys(env);
415
416
/* Validity of stlb_ps is checked in helper_csrwr_stlbps() */
405
- stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
406
- asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
417
+ stlb_ps = FIELD_EX64(sys->CSR_STLBPS, CSR_STLBPS, PS);
418
+ asid = FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID);
419
if (pagesize == stlb_ps) {
420
/* Only write into STLB bits [47:13] */
421
address = addr & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
@@ -461,15 +473,16 @@ void helper_tlbfill(CPULoongArchState *env)
473
vaddr entryhi;
474
int index, pagesize;
475
MMUContext context;
476
+ CPUSysState *sys = env_sys(env);
477
465
- if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
466
- entryhi = env->CSR_TLBREHI;
478
+ if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
479
+ entryhi = sys->CSR_TLBREHI;
480
/* Validity of pagesize is checked in helper_ldpte() */
468
- pagesize = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
481
+ pagesize = FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI, PS);
482
} else {
470
- entryhi = env->CSR_TLBEHI;
483
+ entryhi = sys->CSR_TLBEHI;
484
/* Validity of pagesize is checked in helper_tlbrd() */
472
- pagesize = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
485
+ pagesize = FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, PS);
486
}
487
488
sptw_prepare_context(env, &context);
@@ -483,9 +496,10 @@ void helper_tlbclr(CPULoongArchState *env)
496
LoongArchTLB *tlb;
497
int i, index;
498
uint16_t csr_asid, tlb_asid, tlb_g;
499
+ CPUSysState *sys = env_sys(env);
500
487
- csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
488
- index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
501
+ csr_asid = FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID);
502
+ index = FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX);
503
504
if (index < LOONGARCH_STLB) {
505
/* STLB. One line per operation */
@@ -515,8 +529,9 @@ void helper_tlbclr(CPULoongArchState *env)
529
void helper_tlbflush(CPULoongArchState *env)
530
{
531
int i, index;
532
+ CPUSysState *sys = env_sys(env);
533
519
- index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
534
+ index = FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX);
535
536
if (index < LOONGARCH_STLB) {
537
/* STLB. One line per operation */
@@ -711,6 +726,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
726
uint64_t palen_mask = loongarch_palen_mask(env);
727
uint64_t dir_base, dir_width;
728
uint64_t val;
729
+ CPUSysState *sys = env_sys(env);
730
731
if (unlikely((level == 0) || (level > 4))) {
732
qemu_log_mask(LOG_GUEST_ERROR,
@@ -732,7 +748,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
748
}
749
}
750
735
- badvaddr = env->CSR_TLBRBADV;
751
+ badvaddr = sys->CSR_TLBRBADV;
752
base = base & palen_mask;
753
get_dir_base_width(env, &dir_base, &dir_width, level);
754
index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);
@@ -747,10 +763,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
763
{
764
CPUState *cs = env_cpu(env);
765
hwaddr phys, tmp0, ptindex, ptoffset0, ptoffset1;
766
+ CPUSysState *sys = env_sys(env);
767
uint64_t pte_raw;
768
uint64_t badv;
752
- uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
753
- uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
769
+ uint64_t ptbase = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, PTBASE);
770
+ uint64_t ptwidth = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, PTWIDTH);
771
uint64_t palen_mask = loongarch_palen_mask(env);
772
uint64_t dir_base, dir_width;
773
uint8_t ps;
@@ -796,7 +813,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
813
return;
814
}
815
} else {
799
- badv = env->CSR_TLBRBADV;
816
+ badv = sys->CSR_TLBRBADV;
817
818
base = base & palen_mask;
819
@@ -812,11 +829,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
829
}
830
831
if (odd) {
815
- env->CSR_TLBRELO1 = tmp0;
832
+ sys->CSR_TLBRELO1 = tmp0;
833
} else {
817
- env->CSR_TLBRELO0 = tmp0;
834
+ sys->CSR_TLBRELO0 = tmp0;
835
}
819
- env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
836
+ sys->CSR_TLBREHI = FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
837
}
838
839
static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,