target/arm: Split decode of BFloat SVE FADD, FSUB, FMUL, FMIN*, FMAX*
Split decode so that feature detection can be handled external to gen_gvec_fpst_arg_zpzz Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:41 UTC
f2bfb1cf35bd9684adbe6305b433de15cb7162ef
2 files changed
+52
-18
target/arm/tcg/sve.decode
+31
-7
@@ -159,6 +159,9 @@
159
@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
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@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
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+@rdn_pg_rm_e0 ........ .. ... ... ... pg:3 rm:5 rd:5 \
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+ &rprr_esz esz=0 rn=%reg_movprfx
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+
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# Three register operand, with governing predicate, vector element size
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@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
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&rprrr_esz ra=%reg_movprfx
@@ -1163,14 +1166,35 @@ FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
1166
### SVE FP Arithmetic Predicated Group
1167
1168
# SVE floating-point arithmetic (predicated)
1166
-FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
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-FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
1168
-FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
1169
+{
1170
+ BFADD_zpzz 01100101 00 00 0000 100 ... ..... ..... @rdn_pg_rm_e0
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+ FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
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+}
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+{
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+ BFSUB_zpzz 01100101 00 00 0001 100 ... ..... ..... @rdn_pg_rm_e0
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+ FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
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+}
1177
+{
1178
+ BFMUL_zpzz 01100101 00 00 0010 100 ... ..... ..... @rdn_pg_rm_e0
1179
+ FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
1180
+}
1181
FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
1170
-FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
1171
-FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
1172
-FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
1173
-FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
1182
+{
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+ BFMAXNM_zpzz 01100101 00 00 0100 100 ... ..... ..... @rdn_pg_rm_e0
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+ FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
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+}
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+{
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+ BFMINNM_zpzz 01100101 00 00 0101 100 ... ..... ..... @rdn_pg_rm_e0
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+ FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
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+}
1190
+{
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+ BFMAX_zpzz 01100101 00 00 0110 100 ... ..... ..... @rdn_pg_rm_e0
1192
+ FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
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+}
1194
+{
1195
+ BFMIN_zpzz 01100101 00 00 0111 100 ... ..... ..... @rdn_pg_rm_e0
1196
+ FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
1197
+}
1198
FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
1199
FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
1200
FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
target/arm/tcg/translate-sve.c
+21
-11
@@ -412,10 +412,6 @@ static bool gen_gvec_fpst_zzzp(DisasContext *s, gen_helper_gvec_4_ptr *fn,
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static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
413
arg_rprr_esz *a)
414
{
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- /* These insns use MO_8 to encode BFloat16. */
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- if (a->esz == MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) {
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- return false;
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- }
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return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0,
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a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
417
}
@@ -4426,65 +4422,79 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz,
4422
*/
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static gen_helper_gvec_4_ptr * const sve_fadd_zpzz_fns[4] = {
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- gen_helper_sve_fadd_b16,
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+ NULL,
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gen_helper_sve_fadd_h,
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gen_helper_sve_fadd_s,
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gen_helper_sve_fadd_d
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};
4430
+TRANS_FEAT(BFADD_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
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+ gen_helper_sve_fadd_b16, a)
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TRANS_FEAT(FADD_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fadd_zpzz_fns[a->esz], a)
4434
4435
static gen_helper_gvec_4_ptr * const sve_fsub_zpzz_fns[4] = {
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- gen_helper_sve_fsub_b16,
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+ NULL,
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gen_helper_sve_fsub_h,
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gen_helper_sve_fsub_s,
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gen_helper_sve_fsub_d
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};
4441
+TRANS_FEAT(BFSUB_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
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+ gen_helper_sve_fsub_b16, a)
4443
TRANS_FEAT(FSUB_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fsub_zpzz_fns[a->esz], a)
4445
4446
static gen_helper_gvec_4_ptr * const sve_fmul_zpzz_fns[4] = {
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- gen_helper_sve_fmul_b16,
4447
+ NULL,
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gen_helper_sve_fmul_h,
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gen_helper_sve_fmul_s,
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gen_helper_sve_fmul_d
4451
};
4452
+TRANS_FEAT(BFMUL_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
4453
+ gen_helper_sve_fmul_b16, a)
4454
TRANS_FEAT(FMUL_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fmul_zpzz_fns[a->esz], a)
4456
4457
static gen_helper_gvec_4_ptr * const sve_fmin_fns[4][2] = {
4456
- { gen_helper_sve_fmin_b16, gen_helper_sve_ah_fmin_b16 },
4458
+ { NULL, NULL },
4459
{ gen_helper_sve_fmin_h, gen_helper_sve_ah_fmin_h },
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{ gen_helper_sve_fmin_s, gen_helper_sve_ah_fmin_s },
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{ gen_helper_sve_fmin_d, gen_helper_sve_ah_fmin_d },
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};
4463
+TRANS_FEAT(BFMIN_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
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+ s->fpcr_ah ? gen_helper_sve_ah_fmin_b16 : gen_helper_sve_fmin_b16, a)
4465
TRANS_FEAT(FMIN_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fmin_fns[a->esz][s->fpcr_ah], a)
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static gen_helper_gvec_4_ptr * const sve_fmax_fns[4][2] = {
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- { gen_helper_sve_fmax_b16, gen_helper_sve_ah_fmax_b16 },
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+ { NULL, NULL },
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{ gen_helper_sve_fmax_h, gen_helper_sve_ah_fmax_h },
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{ gen_helper_sve_fmax_s, gen_helper_sve_ah_fmax_s },
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{ gen_helper_sve_fmax_d, gen_helper_sve_ah_fmax_d },
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};
4474
+TRANS_FEAT(BFMAX_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
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+ s->fpcr_ah ? gen_helper_sve_ah_fmax_b16 : gen_helper_sve_fmax_b16, a)
4476
TRANS_FEAT(FMAX_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fmax_fns[a->esz][s->fpcr_ah], a)
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static gen_helper_gvec_4_ptr * const sve_fmaxnum_fns[4] = {
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- gen_helper_sve_fmaxnum_b16,
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+ NULL,
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gen_helper_sve_fmaxnum_h,
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gen_helper_sve_fmaxnum_s,
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gen_helper_sve_fmaxnum_d
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};
4485
+TRANS_FEAT(BFMAXNM_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
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+ gen_helper_sve_fmaxnum_b16, a)
4487
TRANS_FEAT(FMAXNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fmaxnum_fns[a->esz], a)
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4490
static gen_helper_gvec_4_ptr * const sve_fminnum_fns[4] = {
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- gen_helper_sve_fminnum_b16,
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+ NULL,
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gen_helper_sve_fminnum_h,
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gen_helper_sve_fminnum_s,
4494
gen_helper_sve_fminnum_d
4495
};
4496
+TRANS_FEAT(BFMINNM_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz,
4497
+ gen_helper_sve_fminnum_b16, a)
4498
TRANS_FEAT(FMINNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fminnum_fns[a->esz], a)
4500