docs: add MTE4 features to docs
The implemented MTE4 features are now present in docs/system/arm/emulation.rst Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260529-feat-mte4-v7-13-ccbd3c14eb3c@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gabriel Brookman committed
May 29, 2026 at 12:52 UTC
f35b6418ccebf5860d8259c1ae3fc2335f618793
2 files changed
+10
docs/system/arm/emulation.rst
+5
@@ -114,6 +114,11 @@ the following architecture extensions:
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- FEAT_MTE3 (MTE Asymmetric Fault Handling)
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- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
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- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
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+- FEAT_MTE_CANONICAL_TAGS (Canonical tag checking)
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+- FEAT_MTE_NO_ADDRESS_TAGS (Address tagging disabled)
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+- FEAT_MTE_PERM (NoTagAccess memory attribute)
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+- FEAT_MTE_STORE_ONLY (Store-only tag checking)
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+- FEAT_MTE_TAGGED_FAR (Full address reporting of Tag Check Fault)
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- FEAT_NMI (Non-maskable Interrupt)
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- FEAT_NV (Nested Virtualization)
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- FEAT_NV2 (Enhanced nested virtualization support)
target/arm/tcg/cpu64.c
+5
@@ -1296,10 +1296,15 @@ void aarch64_max_tcg_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
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t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
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t = FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */
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+ /* FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */
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+ t = FIELD_DP64(t, ID_AA64PFR1, MTEX, 1);
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SET_IDREG(isar, ID_AA64PFR1, t);
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t = GET_IDREG(isar, ID_AA64PFR2);
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t = FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* FEAT_FPMR */
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+ t = FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* FEAT_MTE_TAGGED_FAR */
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+ t = FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* FEAT_MTE_STORE_ONLY */
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+ t = FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* FEAT_MTE_PERM */
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SET_IDREG(isar, ID_AA64PFR2, t);
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t = GET_IDREG(isar, ID_AA64MMFR0);