target/arm: Setup new registers for GPC3
Adds GPCBW_EL3. A custom write function is necessary to flush TLBs when this register is written. Also allows write to the GPCBW bit of GPCCR_EL3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> Message-id: 20260618-jmac-gpc3b-v3-2-353e546067e7@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jim MacArthur committed
Jun 18, 2026 at 17:33 UTC
f3bd96f8f2d036268526ac2e24a89c1e014df271
2 files changed
+26
target/arm/cpu.h
+7
@@ -559,6 +559,7 @@ typedef struct CPUArchState {
559
/* RME registers */
560
uint64_t gpccr_el3;
561
uint64_t gptbr_el3;
562
+ uint64_t gpcbw_el3;
563
uint64_t mfar_el3;
564
565
/* NV2 register */
@@ -1244,6 +1245,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1245
typedef struct ARMGranuleProtectionConfig {
1246
/* GPCCR_EL3 */
1247
uint64_t gpccr;
1248
+ /* GPCBW_EL3 */
1249
+ uint64_t gpcbw;
1250
/* GPTBR_EL3 */
1251
uint64_t gptbr;
1252
/* ID_AA64MMFR0_EL1.PARange */
@@ -2116,6 +2119,10 @@ FIELD(GPCCR, NA6, 27, 1)
2119
FIELD(GPCCR, NA7, 28, 1)
2120
FIELD(GPCCR, GPCBW, 29, 1)
2121
2122
+FIELD(GPCBW, BWSIZE, 37, 2)
2123
+FIELD(GPCBW, BWSTRIDE, 32, 5)
2124
+FIELD(GPCBW, BWADDR, 0, 25)
2125
+
2126
FIELD(MFAR, FPA, 12, 40)
2127
FIELD(MFAR, NSE, 62, 1)
2128
FIELD(MFAR, NS, 63, 1)
target/arm/helper.c
+19
@@ -5001,6 +5001,10 @@ static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
5001
R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | R_GPCCR_RLPAD_MASK;
5002
}
5003
5004
+ if (cpu_isar_feature(aa64_rme_gpc3, env_archcpu(env))) {
5005
+ rw_mask |= R_GPCCR_GPCBW_MASK;
5006
+ }
5007
+
5008
env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask);
5009
}
5010
@@ -5010,11 +5014,26 @@ static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
5014
env_archcpu(env)->reset_l0gptsz);
5015
}
5016
5017
+static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri,
5018
+ uint64_t value)
5019
+{
5020
+ uint64_t rw_mask = R_GPCBW_BWADDR_MASK | R_GPCBW_BWSTRIDE_MASK |
5021
+ R_GPCBW_BWSIZE_MASK;
5022
+ ARMCPU *cpu = env_archcpu(env);
5023
+
5024
+ tlb_flush(CPU(cpu));
5025
+ env->cp15.gpcbw_el3 = (value & rw_mask);
5026
+}
5027
+
5028
static const ARMCPRegInfo rme_reginfo[] = {
5029
{ .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
5030
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
5031
.access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset,
5032
.fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) },
5033
+ { .name = "GPCBW_EL3", .state = ARM_CP_STATE_AA64,
5034
+ .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 5,
5035
+ .access = PL3_RW, .writefn = gpcbw_write,
5036
+ .fieldoffset = offsetof(CPUARMState, cp15.gpcbw_el3) },
5037
{ .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64,
5038
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
5039
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },