target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207
PPC2_BCTAR_ISA207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_BCTAR_ISA207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-32-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Chinmay Rath committed
Aug 27, 2026 at 18:59 UTC
f475b8f99f832fb6f0c6dcefc1b289dc0d6a8b34
5 files changed
+7
-10
linux-user/ppc/elfload.c
+3
-4
@@ -116,10 +116,9 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
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do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
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GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
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- GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR);
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- GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
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- PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07 |
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- QEMU_PPC_FEATURE2_VEC_CRYPTO);
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+ GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
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+ PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
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+ QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR));
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GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
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QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128);
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GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 |
target/ppc/cpu.h
+1
-3
@@ -2577,8 +2577,6 @@ enum {
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PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
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/* ISA 2.06B floating point test instructions */
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PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
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- /* ISA 2.07 bctar instruction */
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- PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
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/* ISA 2.07 load/store quadword */
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PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
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/* ISA 2.07 Altivec */
@@ -2610,7 +2608,7 @@ enum {
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PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
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PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
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PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
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- PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
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+ PPC2_LSQ_ISA207 | \
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PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
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PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
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PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
target/ppc/cpu_init.c
+1
-1
@@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
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pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
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PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
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- PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
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+ PPC2_FP_TST_ISA206 |
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PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
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PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
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PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
target/ppc/cpu_init.h
+1
-1
@@ -17,7 +17,7 @@
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#define PPC_INSNS_FLAGS2_POWER_COMMON \
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(PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
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- PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \
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+ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
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PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \
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PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
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PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
target/ppc/translate/branch-impl.c.inc
+1
-1
@@ -210,4 +210,4 @@ static bool bclr_helper(DisasContext *ctx, arg_bclr *a, int type)
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TRANS(BCLR, bclr_helper, BCOND_LR)
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TRANS(BCCTR, bclr_helper, BCOND_CTR)
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-TRANS_FLAGS2(BCTAR_ISA207, BCTAR, bclr_helper, BCOND_TAR)
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+TRANS_FLAGS2(ISA207, BCTAR, bclr_helper, BCOND_TAR)