target/arm: Implement FMMLA (FP8 to FP32) for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-42-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:21 UTC
f47a3cca945ef5c86729e1ab58f20aae90bf2239
3 files changed
+23
target/arm/cpu-features.h
+5
@@ -1718,6 +1718,11 @@ static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
1718
return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id);
1719
}
1720
1721
+static inline bool isar_feature_aa64_sve2_f8mm8(const ARMISARegisters *id)
1722
+{
1723
+ return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm8(id);
1724
+}
1725
+
1726
static inline bool
1727
isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)
1728
{
target/arm/tcg/sve.decode
+2
@@ -1808,6 +1808,8 @@ BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=1
1808
FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2
1809
FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3
1810
1811
+FMMLA_sb 01100100 00 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=2
1812
+
1813
### SVE2 Memory Gather Load Group
1814
1815
# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)
target/arm/tcg/translate-sve.c
+16
@@ -8461,3 +8461,19 @@ static bool do_f8dp2(DisasContext *s, gen_helper_gvec_3_ptr *fn,
8461
TRANS(FDOT_hb, do_f8dp2, gen_helper_gvec_fdot_hb, a->rd, a->rn, a->rm, 0)
8462
TRANS(FDOT_idx_hb, do_f8dp2, gen_helper_gvec_fdot_idx_hb,
8463
a->rd, a->rn, a->rm, a->index)
8464
+
8465
+static bool do_fmmla_fp8(DisasContext *s, arg_rrrr_esz *a,
8466
+ gen_helper_gvec_3_ptr *fn)
8467
+{
8468
+ if (fpmr_access_check(s) && sve_access_check(s)) {
8469
+ unsigned vsz = vec_full_reg_size(s);
8470
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
8471
+ vec_full_reg_offset(s, a->rn),
8472
+ vec_full_reg_offset(s, a->rm),
8473
+ tcg_env, vsz, vsz, 0, fn);
8474
+ }
8475
+ return true;
8476
+}
8477
+
8478
+TRANS_FEAT_NONSTREAMING(FMMLA_sb, aa64_sve2_f8mm8, do_fmmla_fp8, a,
8479
+ gen_helper_gvec_fmmla_sb)