@samitouri / QOSamiQemu / commits / f82b564a1f

target/riscv: Fix size of retxh

128-bit helpers only make sense for MXL_RV128, TARGET_RISCV64, and TCGv == TCGv_i64, therefore fix retxh to 64 bits. For the sake of being pedandic, update 128-bit instructions to access retxh via 64 bit TCG ops, even if they only make sense when TCGv == TCGv_i64. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-9-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Anton Johansson committed May 20, 2026 at 14:53 UTC f82b564a1f90ee28777ccac50b1ebec0c311c0b2

3 files changed +19 -7

target/riscv/cpu.h

+1 -1

@@ -250,7 +250,7 @@ struct CPUArchState {

250 uint32_t xl; /* current xlen */

251

252 /* 128-bit helpers upper part return value */

253 - target_ulong retxh;

253 + uint64_t retxh;

254

255 uint64_t jvt;

256

target/riscv/insn_trans/trans_rvi.c.inc

+6 -2

@@ -1030,10 +1030,12 @@ static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)

1030 TCGv destl = dest_gpr(ctx, rd);

1031 TCGv desth = dest_gprh(ctx, rd);

1032 TCGv_i32 csr = tcg_constant_i32(rc);

1033 + TCGv_i64 wide_desth = tcg_temp_new_i64();

1034

1035 translator_io_start(&ctx->base);

1036 gen_helper_csrr_i128(destl, tcg_env, csr);

1036 - tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));

1037 + tcg_gen_ld_i64(wide_desth, tcg_env, offsetof(CPURISCVState, retxh));

1038 + tcg_gen_trunc_i64_tl(desth, wide_desth);

1039 gen_set_gpr128(ctx, rd, destl, desth);

1040 return do_csr_post(ctx);

1041 }

@@ -1053,10 +1055,12 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,

1055 TCGv destl = dest_gpr(ctx, rd);

1056 TCGv desth = dest_gprh(ctx, rd);

1057 TCGv_i32 csr = tcg_constant_i32(rc);

1058 + TCGv_i64 wide_desth = tcg_temp_new_i64();

1059

1060 translator_io_start(&ctx->base);

1061 gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh);

1059 - tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));

1062 + tcg_gen_ld_i64(wide_desth, tcg_env, offsetof(CPURISCVState, retxh));

1063 + tcg_gen_trunc_i64_tl(desth, wide_desth);

1064 gen_set_gpr128(ctx, rd, destl, desth);

1065 return do_csr_post(ctx);

1066 }

target/riscv/insn_trans/trans_rvm.c.inc

+12 -4

@@ -169,8 +169,10 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)

169 static void gen_div_i128(TCGv rdl, TCGv rdh,

170 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)

171 {

172 + TCGv_i64 wide_rdh = tcg_temp_new_i64();

173 gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);

173 - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));

174 + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh));

175 + tcg_gen_trunc_i64_tl(rdh, wide_rdh);

176 }

177

178 static void gen_div(TCGv ret, TCGv source1, TCGv source2)

@@ -212,8 +214,10 @@ static bool trans_div(DisasContext *ctx, arg_div *a)

214 static void gen_divu_i128(TCGv rdl, TCGv rdh,

215 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)

216 {

217 + TCGv_i64 wide_rdh = tcg_temp_new_i64();

218 gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);

216 - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));

219 + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh));

220 + tcg_gen_trunc_i64_tl(rdh, wide_rdh);

221 }

222

223 static void gen_divu(TCGv ret, TCGv source1, TCGv source2)

@@ -244,8 +248,10 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a)

248 static void gen_rem_i128(TCGv rdl, TCGv rdh,

249 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)

250 {

251 + TCGv_i64 wide_rdh = tcg_temp_new_i64();

252 gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);

248 - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));

253 + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh));

254 + tcg_gen_trunc_i64_tl(rdh, wide_rdh);

255 }

256

257 static void gen_rem(TCGv ret, TCGv source1, TCGv source2)

@@ -289,8 +295,10 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a)

295 static void gen_remu_i128(TCGv rdl, TCGv rdh,

296 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)

297 {

298 + TCGv_i64 wide_rdh = tcg_temp_new_i64();

299 gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);

293 - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));

300 + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh));

301 + tcg_gen_trunc_i64_tl(rdh, wide_rdh);

302 }

303

304 static void gen_remu(TCGv ret, TCGv source1, TCGv source2)