target/i386/mshv: migrate CET/SS MSRs
This change migrates the MSRs required for CET shadow stack and indirect branch tracking. They are gated behind cet_ss_support || cet_ibt_support mshv processor feature flags. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-24-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Magnus Kulke committed
Apr 17, 2026 at 12:56 UTC
f879d781b4d8e29ab81db71db6723083c2fe5482
2 files changed
+41
include/hw/hyperv/hvgdk_mini.h
+11
@@ -170,6 +170,17 @@ typedef enum hv_register_name {
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HV_X64_REGISTER_SPEC_CTRL = 0x00080084,
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HV_X64_REGISTER_TSC_ADJUST = 0x00080096,
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+ /* CET / Shadow Stack */
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+ HV_X64_REGISTER_U_XSS = 0x0008008B,
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+ HV_X64_REGISTER_U_CET = 0x0008008C,
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+ HV_X64_REGISTER_S_CET = 0x0008008D,
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+ HV_X64_REGISTER_SSP = 0x0008008E,
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+ HV_X64_REGISTER_PL0_SSP = 0x0008008F,
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+ HV_X64_REGISTER_PL1_SSP = 0x00080090,
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+ HV_X64_REGISTER_PL2_SSP = 0x00080091,
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+ HV_X64_REGISTER_PL3_SSP = 0x00080092,
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+ HV_X64_REGISTER_INTERRUPT_SSP_TABLE_ADDR = 0x00080093,
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+
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/* Other MSRs */
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HV_X64_REGISTER_MSR_IA32_MISC_ENABLE = 0x000800A0,
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target/i386/mshv/msr.c
+30
@@ -81,6 +81,26 @@ static const MshvMsrEnvMap msr_env_map[] = {
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{ IA32_MSR_MTRR_DEF_TYPE, HV_X64_REGISTER_MSR_MTRR_DEF_TYPE,
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offsetof(CPUX86State, mtrr_deftype) },
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+ /* CET / Shadow Stack */
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+ { MSR_IA32_U_CET, HV_X64_REGISTER_U_CET,
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+ offsetof(CPUX86State, u_cet) },
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+ { MSR_IA32_S_CET, HV_X64_REGISTER_S_CET,
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+ offsetof(CPUX86State, s_cet) },
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+ { MSR_IA32_PL0_SSP, HV_X64_REGISTER_PL0_SSP,
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+ offsetof(CPUX86State, pl0_ssp) },
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+ { MSR_IA32_PL1_SSP, HV_X64_REGISTER_PL1_SSP,
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+ offsetof(CPUX86State, pl1_ssp) },
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+ { MSR_IA32_PL2_SSP, HV_X64_REGISTER_PL2_SSP,
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+ offsetof(CPUX86State, pl2_ssp) },
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+ { MSR_IA32_PL3_SSP, HV_X64_REGISTER_PL3_SSP,
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+ offsetof(CPUX86State, pl3_ssp) },
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+ { MSR_IA32_INT_SSP_TAB, HV_X64_REGISTER_INTERRUPT_SSP_TABLE_ADDR,
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+ offsetof(CPUX86State, int_ssp_table) },
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+
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+ /* XSAVE Supervisor State */
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+ { MSR_IA32_XSS, HV_X64_REGISTER_U_XSS,
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+ offsetof(CPUX86State, xss) },
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+
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/* Other */
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/* TODO: find out processor features that correlate to unsupported MSRs. */
@@ -287,6 +307,16 @@ static bool msr_supported(uint32_t name)
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return mshv_state->processor_features.ibrs_support;
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case HV_X64_REGISTER_TSC_ADJUST:
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return mshv_state->processor_features.tsc_adjust_support;
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+ case HV_X64_REGISTER_U_CET:
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+ case HV_X64_REGISTER_S_CET:
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+ case HV_X64_REGISTER_PL0_SSP:
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+ case HV_X64_REGISTER_PL1_SSP:
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+ case HV_X64_REGISTER_PL2_SSP:
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+ case HV_X64_REGISTER_PL3_SSP:
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+ case HV_X64_REGISTER_INTERRUPT_SSP_TABLE_ADDR:
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+ case HV_X64_REGISTER_U_XSS:
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+ return mshv_state->processor_features.cet_ss_support ||
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+ mshv_state->processor_features.cet_ibt_support;
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}
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return true;