target/riscv: Check PMP before updating PTE
According to the RISC-V spec, the PTE update is a supervisor write operations, and it should also follow the CPU PMP configuration like the PTE read. Cc: qemu-stable@nongnu.org Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260622113402.563196-1-inochiama@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Inochi Amaoto committed
Jun 22, 2026 at 19:34 UTC
fa2cf7488379d9b14041a7bcd76867c9bdad2b5e
1 file changed
+8
target/riscv/cpu_helper.c
+8
@@ -1655,10 +1655,18 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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/* Page table updates need to be atomic with MTTCG enabled */
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if (updated_pte != pte && !is_debug) {
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+ int pmp_prot, pmp_ret;
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+
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if (!adue) {
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return TRANSLATE_FAIL;
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}
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+ pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
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+ sxlen_bytes, MMU_DATA_STORE, PRV_S);
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+ if (pmp_ret != TRANSLATE_SUCCESS) {
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+ return TRANSLATE_PMP_FAIL;
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+ }
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+
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/*
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* - if accessed or dirty bits need updating, and the PTE is
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* in RAM, then we do so atomically with a compare and swap.