target/ppc: Move Condition Register logical instructions to decodetree.
Move below instructions to decodetree specification : cr{and, or, xor, nand, nor, eqv, andc, orc} : XL-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-22-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Shivang Upadhyay committed
Aug 27, 2026 at 18:59 UTC
fa4d67fc6d734dddbb1d1f38f11a1e42a160aa54
3 files changed
+56
-59
target/ppc/insn32.decode
+11
@@ -516,6 +516,17 @@ CFUGED 011111 ..... ..... ..... 0011011100 - @X
516
PDEPD 011111 ..... ..... ..... 0010011100 - @X
517
PEXTD 011111 ..... ..... ..... 0010111100 - @X
518
519
+## Condition Register Instructions
520
+
521
+CRAND 010011 ..... ..... ..... 0100000001 - @X
522
+CROR 010011 ..... ..... ..... 0111000001 - @X
523
+CRNAND 010011 ..... ..... ..... 0011100001 - @X
524
+CRXOR 010011 ..... ..... ..... 0011000001 - @X
525
+CRNOR 010011 ..... ..... ..... 0000100001 - @X
526
+CREQV 010011 ..... ..... ..... 0100100001 - @X
527
+CRANDC 010011 ..... ..... ..... 0010000001 - @X
528
+CRORC 010011 ..... ..... ..... 0110100001 - @X
529
+
530
# Fixed-Point Hash Instructions
531
532
HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
target/ppc/translate.c
-59
@@ -2920,53 +2920,6 @@ static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
2920
tcg_gen_movi_tl(cpu_lr, nip);
2921
}
2922
2923
-/*** Condition register logical ***/
2924
-#define GEN_CRLOGIC(name, tcg_op, opc) \
2925
-static void glue(gen_, name)(DisasContext *ctx) \
2926
-{ \
2927
- uint8_t bitmask; \
2928
- int sh; \
2929
- TCGv_i32 t0, t1; \
2930
- sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
2931
- t0 = tcg_temp_new_i32(); \
2932
- if (sh > 0) \
2933
- tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
2934
- else if (sh < 0) \
2935
- tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
2936
- else \
2937
- tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
2938
- t1 = tcg_temp_new_i32(); \
2939
- sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
2940
- if (sh > 0) \
2941
- tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
2942
- else if (sh < 0) \
2943
- tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
2944
- else \
2945
- tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
2946
- tcg_op(t0, t0, t1); \
2947
- bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
2948
- tcg_gen_andi_i32(t0, t0, bitmask); \
2949
- tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
2950
- tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
2951
-}
2952
-
2953
-/* crand */
2954
-GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
2955
-/* crandc */
2956
-GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
2957
-/* creqv */
2958
-GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
2959
-/* crnand */
2960
-GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
2961
-/* crnor */
2962
-GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
2963
-/* cror */
2964
-GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
2965
-/* crorc */
2966
-GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
2967
-/* crxor */
2968
-GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
2969
-
2923
/*** System linkage ***/
2924
2925
/* rfi (supervisor only) */
@@ -5109,18 +5062,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
5062
GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)
5063
#endif
5064
5112
-#undef GEN_CRLOGIC
5113
-#define GEN_CRLOGIC(name, tcg_op, opc) \
5114
-GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
5115
-GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
5116
-GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
5117
-GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
5118
-GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
5119
-GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
5120
-GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
5121
-GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
5122
-GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
5123
-
5065
#undef GEN_MAC_HANDLER
5066
#define GEN_MAC_HANDLER(name, opc2, opc3) \
5067
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
target/ppc/translate/fixedpoint-impl.c.inc
+45
@@ -539,6 +539,51 @@ static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a)
539
return true;
540
}
541
542
+static bool cr_logic_common(DisasContext *ctx, arg_X *a,
543
+ void (*tcg_op)(TCGv_i32, TCGv_i32, TCGv_i32))
544
+{
545
+ uint8_t bitmask;
546
+ int sh;
547
+ TCGv_i32 t0, t1;
548
+ sh = (a->rt & 0x03) - (a->ra & 0x03);
549
+ t0 = tcg_temp_new_i32();
550
+ t1 = tcg_temp_new_i32();
551
+
552
+ if (sh > 0) {
553
+ tcg_gen_shri_i32(t0, cpu_crf[a->ra >> 2], sh);
554
+ } else if (sh < 0) {
555
+ tcg_gen_shli_i32(t0, cpu_crf[a->ra >> 2], -sh);
556
+ } else {
557
+ tcg_gen_mov_i32(t0, cpu_crf[a->ra >> 2]);
558
+ }
559
+
560
+ sh = (a->rt & 0x03) - (a->rb & 0x03);
561
+ if (sh > 0) {
562
+ tcg_gen_shri_i32(t1, cpu_crf[a->rb >> 2], sh);
563
+ } else if (sh < 0) {
564
+ tcg_gen_shli_i32(t1, cpu_crf[a->rb >> 2], -sh);
565
+ } else {
566
+ tcg_gen_mov_i32(t1, cpu_crf[a->rb >> 2]);
567
+ }
568
+ tcg_op(t0, t0, t1);
569
+
570
+ bitmask = 0x08 >> (a->rt & 0x03);
571
+ tcg_gen_andi_i32(t0, t0, bitmask);
572
+ tcg_gen_andi_i32(t1, cpu_crf[a->rt >> 2], ~bitmask);
573
+ tcg_gen_or_i32(cpu_crf[a->rt >> 2], t0, t1);
574
+
575
+ return true;
576
+}
577
+
578
+TRANS(CRAND, cr_logic_common, tcg_gen_and_i32);
579
+TRANS(CROR, cr_logic_common, tcg_gen_or_i32);
580
+TRANS(CRXOR, cr_logic_common, tcg_gen_xor_i32);
581
+TRANS(CRNAND, cr_logic_common, tcg_gen_nand_i32);
582
+TRANS(CRNOR, cr_logic_common, tcg_gen_nor_i32);
583
+TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32);
584
+TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32);
585
+TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32);
586
+
587
static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
588
bool compute_ov, bool compute_rc0)
589
{