@samitouri / QOSamiQemu / commits / fae82341be

hw/dma/omap_dma: Remove 3.1 mapping handling

Now we have no 3.2 DMA support, the omap_dma_enable_3_1_mapping() function is called at reset, and there is no longer anywhere that disables it. Remove the function and the unused omap_3_1_mapping_disabled struct field, and drop the indirection from omap_dma_interrupts_update() through the intr_update function pointer to omap_dma_interrupts_3_1_update(), instead inlining that last function into omap_dma_interrupts_update(). The only other thing omap_dma_enable_3_1_mapping() was doing was setting s->chans; since this is now never changed at runtime we can move its setting into the init function rather than reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260512203414.3633237-11-peter.maydell@linaro.org

Peter Maydell committed May 12, 2026 at 21:34 UTC fae82341beb74c16945ee333490c2f836e4adfce

1 file changed +22 -30

hw/dma/omap_dma.c

+22 -30

@@ -106,8 +106,6 @@ struct omap_dma_s {

106 struct omap_mpu_state_s *mpu;

107 omap_clk clk;

108 qemu_irq irq[4];

109 - void (*intr_update)(struct omap_dma_s *s);

110 - int omap_3_1_mapping_disabled;

109

110 uint32_t gcr;

111 uint32_t ocp;

@@ -134,7 +132,27 @@ struct omap_dma_s {

132

133 static inline void omap_dma_interrupts_update(struct omap_dma_s *s)

134 {

137 - s->intr_update(s);

135 + struct omap_dma_channel_s *ch = s->ch;

136 +

137 + /* First three interrupts are shared between two channels each. */

138 + if (ch[0].status | ch[6].status) {

139 + qemu_irq_raise(ch[0].irq);

140 + }

141 + if (ch[1].status | ch[7].status) {

142 + qemu_irq_raise(ch[1].irq);

143 + }

144 + if (ch[2].status | ch[8].status) {

145 + qemu_irq_raise(ch[2].irq);

146 + }

147 + if (ch[3].status) {

148 + qemu_irq_raise(ch[3].irq);

149 + }

150 + if (ch[4].status) {

151 + qemu_irq_raise(ch[4].irq);

152 + }

153 + if (ch[5].status) {

154 + qemu_irq_raise(ch[5].irq);

155 + }

156 }

157

158 static void omap_dma_channel_load(struct omap_dma_channel_s *ch)

@@ -294,32 +312,6 @@ static void omap_dma_channel_end_prog(struct omap_dma_s *s,

312 }

313 }

314

297 -static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)

298 -{

299 - struct omap_dma_channel_s *ch = s->ch;

300 -

301 - /* First three interrupts are shared between two channels each. */

302 - if (ch[0].status | ch[6].status)

303 - qemu_irq_raise(ch[0].irq);

304 - if (ch[1].status | ch[7].status)

305 - qemu_irq_raise(ch[1].irq);

306 - if (ch[2].status | ch[8].status)

307 - qemu_irq_raise(ch[2].irq);

308 - if (ch[3].status)

309 - qemu_irq_raise(ch[3].irq);

310 - if (ch[4].status)

311 - qemu_irq_raise(ch[4].irq);

312 - if (ch[5].status)

313 - qemu_irq_raise(ch[5].irq);

314 -}

315 -

316 -static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)

317 -{

318 - s->omap_3_1_mapping_disabled = 0;

319 - s->chans = 9;

320 - s->intr_update = omap_dma_interrupts_3_1_update;

321 -}

322 -

315 static void omap_dma_process_request(struct omap_dma_s *s, int request)

316 {

317 int channel;

@@ -660,7 +652,6 @@ void omap_dma_reset(struct soc_dma_s *dma)

652 s->lcd_ch.condition = 0;

653 s->lcd_ch.interrupts = 0;

654 s->lcd_ch.dual = 0;

663 - omap_dma_enable_3_1_mapping(s);

655 for (i = 0; i < s->chans; i ++) {

656 s->ch[i].suspend = 0;

657 s->ch[i].prefetch = 0;

@@ -1193,6 +1184,7 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,

1184 s->clk = clk;

1185 s->lcd_ch.irq = lcd_irq;

1186 s->lcd_ch.mpu = mpu;

1187 + s->chans = 9;

1188

1189 s->dma = soc_dma_init(9);

1190 s->dma->freq = omap_clk_getrate(clk);