hw/arm/smmuv3: Enforce alignment of L2Ptr according to the span
Spec says: Bits L2Ptr[N:0] are treated as 0 by the SMMU, where N == 5 + (Span - 1). Let's enforce this alignment. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Message-id: 20260707085028.165557-6-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger committed
Jul 13, 2026 at 12:34 UTC
fb26953ed9d0648ddc854fe6f788bea0c378417b
1 file changed
+2
hw/arm/smmuv3.c
+2
@@ -728,6 +728,8 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event)
728
729
max_l2_ste = (1 << span) - 1;
730
l2ptr = l1std_l2ptr(&l1std);
731
+
732
+ l2ptr &= ~MAKE_64BIT_MASK(0, 6 + (span - 1));
733
trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset,
734
l2ptr, l2_ste_offset, max_l2_ste);
735
if (l2_ste_offset > max_l2_ste) {