target/riscv: Add Zicclsm CPU option and enable it for the eligible CPUs
Add Zicclsm CPU option and enable it for the following eligible CPUs: - Base 32 CPU (to be backward compatible) - Base 64 CPU (to be backward compatible) - XuanTie (T-Head) C908 - Tenstorrent Ascalon - Ventana Veyron V1 - XiangShan Kunminghu - MIPS P8700 (ISA doesn't include Zicclsm, but their datasheet claims that it has unaligned load/store support in hardware) Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260810055618.1175500-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Aug 10, 2026 at 13:56 UTC
fbc151a66ff16153a96af8a836cd64015277972c
2 files changed
+9
target/riscv/cpu.c
+7
@@ -3347,6 +3347,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3347
.cfg.ext_zicbom = true,
3348
.cfg.ext_zicbop = true,
3349
.cfg.ext_zicboz = true,
3350
+ .cfg.ext_zicclsm = true,
3351
.cfg.ext_zicntr = true,
3352
.cfg.ext_zicsr = true,
3353
.cfg.ext_zifencei = true,
@@ -3419,6 +3420,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3420
.cfg.ext_zicbom = true,
3421
.cfg.ext_zicbop = true,
3422
.cfg.ext_zicboz = true,
3423
+ .cfg.ext_zicclsm = true,
3424
.cfg.ext_zicntr = true,
3425
.cfg.ext_zicsr = true,
3426
.cfg.ext_zifencei = true,
@@ -3505,6 +3507,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3507
.cfg.ext_zbs = true,
3508
.cfg.ext_zkt = true,
3509
.cfg.ext_zbkc = true,
3510
+ .cfg.ext_zicclsm = true,
3511
.cfg.ext_zicsr = true,
3512
.cfg.ext_zifencei = true,
3513
.cfg.ext_zihintpause = true,
@@ -3548,6 +3551,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3551
.cfg.ext_zicbom = true,
3552
.cfg.ext_zicbop = true,
3553
.cfg.ext_zicboz = true,
3554
+ .cfg.ext_zicclsm = true,
3555
.cfg.ext_zicntr = true,
3556
.cfg.ext_zicond = true,
3557
.cfg.ext_zicsr = true,
@@ -3597,6 +3601,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3601
3602
/* ISA extensions */
3603
.cfg.mmu = true,
3604
+ .cfg.ext_zicclsm = true,
3605
.cfg.ext_zifencei = true,
3606
.cfg.ext_zicsr = true,
3607
.cfg.pmp = true,
@@ -3656,6 +3661,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3661
* The RISC-V Instruction Set Manual: Volume I
3662
* Unprivileged Architecture
3663
*/
3664
+ .cfg.ext_zicclsm = true,
3665
.cfg.ext_zicntr = true,
3666
.cfg.ext_zihpm = true,
3667
.cfg.ext_zihintntl = true,
@@ -3712,6 +3718,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
3718
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
3719
.priv_spec = PRIV_VERSION_1_12_0,
3720
.cfg.max_satp_mode = VM_1_10_SV48,
3721
+ .cfg.ext_zicclsm = true,
3722
.cfg.ext_zifencei = true,
3723
.cfg.ext_zicsr = true,
3724
.cfg.mmu = true,
target/riscv/cpu_cfg_fields.h.inc
+2
@@ -139,6 +139,8 @@ BOOL_FIELD(has_priv_1_11)
139
/* Always enabled for TCG if has_priv_1_11 */
140
BOOL_FIELD(ext_ziccrse)
141
142
+BOOL_FIELD(ext_zicclsm)
143
+
144
/* Vendor-specific custom extensions */
145
BOOL_FIELD(ext_xtheadba)
146
BOOL_FIELD(ext_xtheadbb)