1364
.endianness = DEVICE_NATIVE_ENDIAN,
1365
};
1366
1367
-static uint64_t memory_region_ram_device_read(void *opaque,
1368
- hwaddr addr, unsigned size)
1369
-{
1370
- MemoryRegion *mr = opaque;
1371
- uint64_t data = ldn_he_p(mr->ram_block->host + addr, size);
1372
-
1373
- trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1374
-
1375
- return data;
1376
-}
1377
-
1378
-static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1379
- uint64_t data, unsigned size)
1380
-{
1381
- MemoryRegion *mr = opaque;
1382
-
1383
- trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1384
-
1385
- stn_he_p(mr->ram_block->host + addr, size, data);
1386
-}
1387
-
1388
-static const MemoryRegionOps ram_device_mem_ops = {
1389
- .read = memory_region_ram_device_read,
1390
- .write = memory_region_ram_device_write,
1391
- .endianness = HOST_BIG_ENDIAN ? DEVICE_BIG_ENDIAN : DEVICE_LITTLE_ENDIAN,
1392
- .valid = {
1393
- .min_access_size = 1,
1394
- .max_access_size = 8,
1395
- .unaligned = true,
1396
- },
1397
- .impl = {
1398
- .min_access_size = 1,
1399
- .max_access_size = 8,
1400
- .unaligned = true,
1401
- },
1402
-};
1403
-
1367
bool memory_region_access_valid(MemoryRegion *mr,
1368
hwaddr addr,
1369
unsigned size,
1655
const char *name, uint64_t size,
1656
void *ptr)
1657
{
1695
- memory_region_init_io(mr, owner, &ram_device_mem_ops, mr, name, size);
1696
- mr->ram = true;
1658
+ memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1659
mr->ram_device = true;
1698
- memory_region_set_ram_ptr(mr, size, ptr);
1660
}
1661
1662
void memory_region_init_alias(MemoryRegion *mr, Object *owner,