target/hexagon: add GVec overrides for HVX vector average
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260807152241.1576334-6-brian.cain@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Aug 7, 2026 at 08:22 UTC
ffbb6bbca5d0b74fb24ece36356963267f8b34ab
1 file changed
+62
target/hexagon/gen_tcg_hvx.h
+62
@@ -342,6 +342,68 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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gen_gvec_sabsdiff(MO_32, VdV_off, VuV_off, VvV_off, \
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VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+#define fGEN_TCG_VEC_AVG(VECE, SHIFT_FN) \
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+ do { \
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+ intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
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+ tcg_gen_gvec_and(MO_64, tmpoff, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ SHIFT_FN(VECE, VdV_off, VdV_off, 1, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ tcg_gen_gvec_add(VECE, VdV_off, tmpoff, VdV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ } while (0)
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+
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+#define fGEN_TCG_V6_vavgub(SHORTCODE) \
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+ fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri)
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+
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+#define fGEN_TCG_V6_vavguh(SHORTCODE) \
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+ fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri)
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+
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+#define fGEN_TCG_V6_vavguw(SHORTCODE) \
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+ fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri)
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+
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+#define fGEN_TCG_V6_vavgb(SHORTCODE) \
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+ fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari)
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+
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+#define fGEN_TCG_V6_vavgh(SHORTCODE) \
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+ fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari)
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+
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+#define fGEN_TCG_V6_vavgw(SHORTCODE) \
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+ fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari)
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+
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+#define fGEN_TCG_VEC_AVGRND(VECE, SHIFT_FN) \
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+ do { \
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+ intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
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+ tcg_gen_gvec_or(MO_64, tmpoff, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ SHIFT_FN(VECE, VdV_off, VdV_off, 1, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ tcg_gen_gvec_sub(VECE, VdV_off, tmpoff, VdV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
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+ } while (0)
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+
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+#define fGEN_TCG_V6_vavgubrnd(SHORTCODE) \
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+ fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri)
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+
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+#define fGEN_TCG_V6_vavguhrnd(SHORTCODE) \
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+ fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri)
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+
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+#define fGEN_TCG_V6_vavguwrnd(SHORTCODE) \
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+ fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri)
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+
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+#define fGEN_TCG_V6_vavgbrnd(SHORTCODE) \
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+ fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari)
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+
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+#define fGEN_TCG_V6_vavghrnd(SHORTCODE) \
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+ fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari)
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+
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+#define fGEN_TCG_V6_vavgwrnd(SHORTCODE) \
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+ fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari)
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+
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/* Vector shift right - various forms */
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#define fGEN_TCG_V6_vasrh(SHORTCODE) \
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do { \