Fix _riscv_supports_rvv_vlen128() to detect RVV on hardware without zvl flags (#43179)
Signed-off-by: liuyudong <liuyudong@iscas.ac.cn> Co-authored-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>
lyd1992 committed
Jun 18, 2026 at 21:22 UTC
021cdf72bc2295b5dcb60fcbc4b0dae66831cf77
3 files changed
+30
-3
csrc/cpu/cpu_attn.cpp
+11
@@ -11,6 +11,17 @@ static inline cpu_attention::Fp8KVCacheDataType parse_fp8_kv_dtype(
11
return cpu_attention::Fp8KVCacheDataType::kAuto;
12
}
13
14
+bool cpu_attn_has_isa(const std::string& isa) {
15
+ if (isa == "rvv") {
16
+#if defined(__riscv) && defined(__riscv_v_min_vlen) && __riscv_v_min_vlen == 128
17
+ return true;
18
+#else
19
+ return false;
20
+#endif
21
+ }
22
+ return false;
23
+}
24
+
25
torch::Tensor get_scheduler_metadata(
26
const int64_t num_req, const int64_t num_heads_q,
27
const int64_t num_heads_kv, const int64_t head_dim,
csrc/cpu/torch_bindings.cpp
+3
@@ -146,6 +146,8 @@ at::Tensor causal_conv1d_update_cpu(
146
void activation_lut_bf16(torch::Tensor& out, torch::Tensor& input,
147
const std::string& activation);
148
149
+bool cpu_attn_has_isa(const std::string& isa);
150
+
151
torch::Tensor get_scheduler_metadata(
152
const int64_t num_req, const int64_t num_heads_q,
153
const int64_t num_heads_kv, const int64_t head_dim,
@@ -497,6 +499,7 @@ TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, ops) {
499
ops.impl("fused_gdn_gating_cpu", torch::kCPU, &fused_gdn_gating_cpu);
500
501
// CPU attention kernels
502
+ ops.def("cpu_attn_has_isa(str isa) -> bool", &cpu_attn_has_isa);
503
ops.def(
504
"get_scheduler_metadata(int num_req, int num_heads_q, int num_heads_kv, "
505
"int head_dim, Tensor seq_lens, ScalarType dtype, Tensor "
vllm/v1/attention/backends/cpu_attn.py
+16
-3
@@ -438,9 +438,22 @@ def _riscv_supports_rvv() -> bool:
438
cpuinfo = f.read()
439
except OSError:
440
return False
441
- return any(f"zvl{n}b" in cpuinfo for n in (128, 256)) and all(
442
- f"zvl{n}b" not in cpuinfo for n in (512, 1024)
443
- )
441
+ # If VLEN >= 512 is detected, the RVV kernel was not compiled.
442
+ if any(f"zvl{n}b" in cpuinfo for n in (512, 1024)):
443
+ return False
444
+
445
+ # zvl128b or zvl256b explicitly advertised -> RVV kernel available.
446
+ if any(f"zvl{n}b" in cpuinfo for n in (128, 256)):
447
+ return True
448
+
449
+ # No zvl<N>b flag at all (e.g. some hardware reports zve* without
450
+ # a VLEN hint). Delegate to the C++ compile-time check instead.
451
+ try:
452
+ import torch
453
+
454
+ return torch.ops._C.cpu_attn_has_isa("rvv")
455
+ except Exception:
456
+ return False
457
458
459
def _get_attn_isa(