[CI/Build] Fix pre-commit check (#47695)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Li, Jiang committed
Jul 6, 2026 at 16:24 UTC
344609ab170a040fe5cfec74eac8db66cd344b6f
1 file changed
+7
-8
csrc/cpu/cpu_types_riscv_impl.hpp
+7
-8
@@ -638,21 +638,20 @@ struct FP32Vec16 : public Vec<FP32Vec16> {
638
const uint32_t hi = static_cast<uint32_t>(q >> 32);
639
640
auto lane_ids = RVVI(__riscv_vid_v_u32, LMUL_256)(HALF);
641
- auto shifts =
642
- RVVI(__riscv_vsll_vx_u32, LMUL_256)(lane_ids, 2, HALF);
641
+ auto shifts = RVVI(__riscv_vsll_vx_u32, LMUL_256)(lane_ids, 2, HALF);
642
643
auto packed_lo = RVVI(__riscv_vmv_v_x_u32, LMUL_256)(lo, HALF);
644
auto idx_lo = RVVI(__riscv_vand_vx_u32, LMUL_256)(
646
- RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_lo, shifts, HALF),
647
- 0xF, HALF);
645
+ RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_lo, shifts, HALF), 0xF,
646
+ HALF);
647
648
auto packed_hi = RVVI(__riscv_vmv_v_x_u32, LMUL_256)(hi, HALF);
649
auto idx_hi = RVVI(__riscv_vand_vx_u32, LMUL_256)(
651
- RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_hi, shifts, HALF),
652
- 0xF, HALF);
650
+ RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_hi, shifts, HALF), 0xF,
651
+ HALF);
652
654
- auto idx = RVVI4(__riscv_vcreate_v_u32, LMUL_256, _u32,
655
- LMUL_512)(idx_lo, idx_hi);
653
+ auto idx =
654
+ RVVI4(__riscv_vcreate_v_u32, LMUL_256, _u32, LMUL_512)(idx_lo, idx_hi);
655
reg = RVVI(__riscv_vrgather_vv_f32, LMUL_512)(lut.reg, idx, VEC_ELEM_NUM);
656
}
657
explicit FP32Vec16(const FP16Vec16& v);