A high-throughput and memory-efficient inference and serving engine for LLMs
Mirrored from https://github.com/tduncan-lum/Nvidia-Optimization-Stack---VLLM.git
Synced Nov 4, 18:45 UTC
[ROCm] Add gfx1102/gfx1103 support (#40037)
Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
Matthias Gehre committed
Apr 23, 2026 at 10:32 UTC
4b7869d6bc64f5b124e2403891b4c2e29713bbf5
3 files changed
+21
-35
CMakeLists.txt
+1
-1
@@ -37,7 +37,7 @@ install(CODE "set(CMAKE_INSTALL_LOCAL_ONLY TRUE)" ALL_COMPONENTS)
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set(PYTHON_SUPPORTED_VERSIONS "3.10" "3.11" "3.12" "3.13")
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# Supported AMD GPU architectures.
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-set(HIP_SUPPORTED_ARCHS "gfx906;gfx908;gfx90a;gfx942;gfx950;gfx1030;gfx1100;gfx1101;gfx1150;gfx1151;gfx1152;gfx1153;gfx1200;gfx1201")
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+set(HIP_SUPPORTED_ARCHS "gfx906;gfx908;gfx90a;gfx942;gfx950;gfx1030;gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151;gfx1152;gfx1153;gfx1200;gfx1201")
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# ROCm installation prefix. Default to /opt/rocm but allow override via
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# -DROCM_PATH=/your/rocm/path when invoking cmake.
csrc/rocm/attention.cu
+2
-11
@@ -40,15 +40,6 @@ using __hip_fp8_e5m2 = __hip_fp8_e5m2_fnuz;
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#define __HIP__FP8MFMA__
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#endif
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-#if defined(__HIPCC__) && (defined(__gfx1100__) || defined(__gfx1101__) || \
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- defined(__gfx1150__) || defined(__gfx1151__))
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- #define __HIP__GFX11__
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-#endif
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-
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-#if defined(__HIPCC__) && (defined(__gfx1200__) || defined(__gfx1201__))
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- #define __HIP__GFX12__
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-#endif
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-
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#if defined(NDEBUG)
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#undef NDEBUG
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#include <assert.h>
@@ -1629,7 +1620,7 @@ __launch_bounds__(NUM_THREADS) void paged_attention_ll4mi_reduce_kernel(
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}
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}
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-#elif defined(__HIP__GFX11__)
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+#elif defined(__GFX11__)
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using floatx8 = __attribute__((__vector_size__(8 * sizeof(float)))) float;
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@@ -2388,7 +2379,7 @@ __launch_bounds__(NUM_THREADS) void paged_attention_ll4mi_reduce_kernel(
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out_ptr[threadIdx.x] = from_float<scalar_t>(acc);
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}
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-#elif defined(__HIP__GFX12__)
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+#elif defined(__GFX12__)
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using floatx8 = __attribute__((__vector_size__(8 * sizeof(float)))) float;
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csrc/rocm/skinny_gemms.cu
+18
-23
@@ -26,16 +26,11 @@
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#define __HIP__GFX9__
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#endif
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-#if defined(__HIPCC__) && \
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- (defined(__gfx1100__) || defined(__gfx1101__) || defined(__gfx1150__) || \
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- defined(__gfx1151__) || defined(__gfx1200__) || defined(__gfx1201__))
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+// Combined RDNA macro (gfx11 + gfx12) - both use 32-wide wavefronts
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+#if defined(__GFX11__) || defined(__GFX12__)
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#define __HIP__GFX1X__
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#endif
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-#if defined(__HIPCC__) && (defined(__gfx1200__) || defined(__gfx1201__))
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- #define __HIP__GFX12__
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-#endif
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-
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#if defined(__HIPCC__) && (defined(__gfx942__) || defined(__gfx950__))
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#define __HIP__MI3XX__
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#endif
@@ -1845,7 +1840,7 @@ torch::Tensor wvSplitKrc(const at::Tensor& in_a, const at::Tensor& in_b,
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return out_c;
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}
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-#if defined(__HIP__MI3XX__) || defined(__HIP__GFX12__)
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+#if defined(__HIP__MI3XX__) || defined(__GFX12__)
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template <typename scalar_t, typename fp8_t, int THRDS, int YTILE, int WvPrGrp,
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int A_CHUNK, int UNRL, int N>
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__global__ void __launch_bounds__(WvPrGrp* THRDS)
@@ -1893,7 +1888,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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float sB = *s_B;
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while (m < M) {
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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// gfx12: per-lane scalar accumulation via v_dot4_f32_fp8_fp8
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float sum[N][YTILE] = {};
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#else
@@ -1931,7 +1926,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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#pragma unroll
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for (uint32_t k2 = 0; k2 < UNRL; k2++) {
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for (uint32_t n = 0; n < N; n++) {
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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// gfx12: 4 x dot4 per A_CHUNK=16 bytes (4 FP8 per dot4)
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for (int y = 0; y < YTILE; ++y) {
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#pragma unroll
@@ -1955,7 +1950,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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}
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// Final reduction
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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// gfx12 wave32: DPP row_shr within 16-lane rows + cross-row shuffle
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for (int n = 0; n < N; n++) {
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for (int y = 0; y < YTILE; y++) {
@@ -1993,7 +1988,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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#endif
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const bool writeback_lane =
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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threadIdx.x == (THRDS - 1);
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#else
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threadIdx.x == 0;
@@ -2009,7 +2004,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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for (int n = 0; n < N; n++) {
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for (int y = 0; y < YTILE; y++) {
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if (y + m >= M) break; // To avoid mem access fault.
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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float result = sum[n][y] * sA * sB;
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#else
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float result = sum[n][y][0] * sA * sB;
@@ -2027,7 +2022,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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m += CuCount * _WvPrGrp * YTILE;
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}
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}
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-#else // !defined(__HIP__MI3XX__) && !defined(__HIP__GFX12__)
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+#else // !defined(__HIP__MI3XX__) && !defined(__GFX12__)
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template <typename scalar_t, typename fp8_t, int THRDS, int YTILE, int WvPrGrp,
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int A_CHUNK, int UNRL, int N>
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__global__ void wvSplitKQ_hf_sml_(const int K, const int Kap, const int Kbp,
@@ -2039,9 +2034,9 @@ __global__ void wvSplitKQ_hf_sml_(const int K, const int Kap, const int Kbp,
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const int _WvPrGrp, const int CuCount) {
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UNREACHABLE_CODE
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}
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-#endif // defined(__HIP__MI3XX__) || defined(__HIP__GFX12__)
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+#endif // defined(__HIP__MI3XX__) || defined(__GFX12__)
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-#if defined(__HIP__MI3XX__) || defined(__HIP__GFX12__)
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+#if defined(__HIP__MI3XX__) || defined(__GFX12__)
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template <typename scalar_t, typename fp8_t, int THRDS, int YTILE, int WvPrGrp,
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int A_CHUNK, int UNRL, int N>
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__global__ void __launch_bounds__(WvPrGrp* THRDS)
@@ -2088,7 +2083,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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float sB = *s_B;
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while (m < M) {
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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// gfx12: per-lane scalar accumulation via v_dot4_f32_fp8_fp8
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float sum[N][YTILE] = {};
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#else
@@ -2128,7 +2123,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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#pragma unroll
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for (uint32_t k2 = 0; k2 < UNRL; k2++) {
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for (uint32_t n = 0; n < N; n++) {
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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// gfx12: 4 x dot4 per A_CHUNK=16 bytes (4 FP8 per dot4)
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for (int y = 0; y < YTILE; ++y) {
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#pragma unroll
@@ -2152,7 +2147,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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}
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// Final reduction
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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// gfx12 wave32: DPP row_shr within 16-lane rows + cross-row shuffle
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for (int n = 0; n < N; n++) {
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for (int y = 0; y < YTILE; y++) {
@@ -2190,7 +2185,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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#endif
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const bool writeback_lane =
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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threadIdx.x == (THRDS - 1);
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#else
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threadIdx.x == 0;
@@ -2206,7 +2201,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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for (int n = 0; n < N; n++) {
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for (int y = 0; y < YTILE; y++) {
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if (y + m >= M) break; // To avoid mem access fault.
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- #ifdef __HIP__GFX12__
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+ #ifdef __GFX12__
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float result = sum[n][y] * sA * sB;
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#else
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float result = sum[n][y][0] * sA * sB;
@@ -2224,7 +2219,7 @@ __global__ void __launch_bounds__(WvPrGrp* THRDS)
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m += CuCount * _WvPrGrp * YTILE;
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}
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}
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-#else // !defined(__HIP__MI3XX__) && !defined(__HIP__GFX12__)
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+#else // !defined(__HIP__MI3XX__) && !defined(__GFX12__)
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template <typename scalar_t, typename fp8_t, int THRDS, int YTILE, int WvPrGrp,
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int A_CHUNK, int UNRL, int N>
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__global__ void wvSplitKQ_hf_(const int K, const int Kap, const int Kbp,
@@ -2236,7 +2231,7 @@ __global__ void wvSplitKQ_hf_(const int K, const int Kap, const int Kbp,
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const int CuCount) {
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UNREACHABLE_CODE
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}
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-#endif // defined(__HIP__MI3XX__) || defined(__HIP__GFX12__)
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+#endif // defined(__HIP__MI3XX__) || defined(__GFX12__)
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void wvSplitKQ(const at::Tensor& in_b, const at::Tensor& in_a,
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const std::optional<at::Tensor>& in_bias, at::Tensor& out_c,