A high-throughput and memory-efficient inference and serving engine for LLMs
Mirrored from https://github.com/tduncan-lum/Nvidia-Optimization-Stack---VLLM.git
Synced Nov 15, 06:00 UTC
[Fix] Allow kernel compilation for CUDA capability 8.7 (#19328)
Signed-off-by: Conroy Cheers <conroy@corncheese.org>
Conroy Cheers committed
Jun 9, 2025 at 19:57 UTC
59abbd84f90e5930c37e205de8849ac4fa8a96c7
1 file changed
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-3
CMakeLists.txt
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-3
@@ -308,7 +308,7 @@ if(VLLM_GPU_LANG STREQUAL "CUDA")
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# Keep building Marlin for 9.0 as there are some group sizes and shapes that
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# are not supported by Machete yet.
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# 9.0 for latest bf16 atomicAdd PTX
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- cuda_archs_loose_intersection(MARLIN_ARCHS "8.0;9.0+PTX" "${CUDA_ARCHS}")
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+ cuda_archs_loose_intersection(MARLIN_ARCHS "8.0;8.7;9.0+PTX" "${CUDA_ARCHS}")
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if (MARLIN_ARCHS)
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#
@@ -454,7 +454,7 @@ if(VLLM_GPU_LANG STREQUAL "CUDA")
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# kernels for the remaining archs that are not already built for 3x.
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# (Build 8.9 for FP8)
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cuda_archs_loose_intersection(SCALED_MM_2X_ARCHS
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- "7.5;8.0;8.9+PTX" "${CUDA_ARCHS}")
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+ "7.5;8.0;8.7;8.9+PTX" "${CUDA_ARCHS}")
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# subtract out the archs that are already built for 3x
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list(REMOVE_ITEM SCALED_MM_2X_ARCHS ${SCALED_MM_3X_ARCHS})
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if (SCALED_MM_2X_ARCHS)
@@ -684,7 +684,7 @@ if(VLLM_GPU_LANG STREQUAL "CUDA")
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list(APPEND VLLM_MOE_EXT_SRC "${VLLM_MOE_WNA16_SRC}")
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# 9.0 for latest bf16 atomicAdd PTX
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- cuda_archs_loose_intersection(MARLIN_MOE_ARCHS "8.0;9.0+PTX" "${CUDA_ARCHS}")
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+ cuda_archs_loose_intersection(MARLIN_MOE_ARCHS "8.0;8.7;9.0+PTX" "${CUDA_ARCHS}")
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if (MARLIN_MOE_ARCHS)
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#