[Bugfix][CPU][RISC-V] Fix build: make FP32Vec copy constructors non-explicit (#51099)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
velonica0 committed
Aug 14, 2026 at 12:59 UTC
ac7509e2b1db40fec2f03dde1ed4e9dfdc2338c9
1 file changed
+6
-2
csrc/cpu/cpu_types_riscv_impl.hpp
+6
-2
@@ -427,7 +427,10 @@ struct FP32Vec8 : public Vec<FP32Vec8> {
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explicit FP32Vec8(const float* ptr)
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: reg(RVVI(__riscv_vle32_v_f32, LMUL_256)(ptr, VEC_ELEM_NUM)) {};
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explicit FP32Vec8(fixed_fp32x8_t data) : reg(data) {};
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- explicit FP32Vec8(const FP32Vec8& data) : reg(data.reg) {};
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+ // Not explicit: copy-initialisation (`auto v = pair.first`) in
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+ // cpu_attn_vec.hpp requires a converting copy constructor, and every other
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+ // CPU backend leaves this implicit.
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+ FP32Vec8(const FP32Vec8& data) : reg(data.reg) {};
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explicit FP32Vec8(const FP16Vec8& v)
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: reg(RVVI(__riscv_vfwcvt_f_f_v_f32, LMUL_256)(v.reg, VEC_ELEM_NUM)) {};
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explicit FP32Vec8(fixed_fp16x8_t v)
@@ -628,7 +631,8 @@ struct FP32Vec16 : public Vec<FP32Vec16> {
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explicit FP32Vec16(const FP32Vec8& data)
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: reg(RVVI4(__riscv_vcreate_v_f32, LMUL_256, _f32, LMUL_512)(
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data.reg, data.reg)) {};
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- explicit FP32Vec16(const FP32Vec16& data) : reg(data.reg) {};
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+ // Not explicit: see FP32Vec8's copy constructor.
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+ FP32Vec16(const FP32Vec16& data) : reg(data.reg) {};
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explicit FP32Vec16(int64_t value, const FP32Vec16& lut) {
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// Split into two 32-bit halves to avoid u64 @ LMUL_1024 (m8 on
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// VLEN=128 / m4 on VLEN=256), which causes heavy register spilling.