A high-throughput and memory-efficient inference and serving engine for LLMs
Mirrored from https://github.com/tduncan-lum/Nvidia-Optimization-Stack---VLLM.git
Synced Nov 14, 05:30 UTC
[Fix] Improve CPU backend compatibility for RISC-V (#25816)
Signed-off-by: lyd1992 <liuyudong@iscas.ac.cn> Signed-off-by: ihb2032 <1355790728@qq.com>
ihb2032 committed
Sep 30, 2025 at 21:48 UTC
bb6d43047e24f29ae5ef9d3abd4c93b447f2f0c7
1 file changed
+5
-4
vllm/engine/arg_utils.py
+5
-4
@@ -1160,11 +1160,12 @@ class EngineArgs:
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# Set default arguments for V1 Engine.
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self._set_default_args(usage_context, model_config)
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- # Disable chunked prefill for POWER (ppc64le)/ARM/s390x CPUs in V1
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+ # Disable chunked prefill for POWER (ppc64le)/ARM/s390x/RISCV CPUs in V1
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if current_platform.is_cpu() and current_platform.get_cpu_architecture(
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- ) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM):
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- logger.info("Chunked prefill is not supported for ARM and POWER "
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- "and S390X CPUs; "
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+ ) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM,
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+ CpuArchEnum.RISCV):
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+ logger.info("Chunked prefill is not supported for ARM and POWER, "
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+ "S390X and RISC-V CPUs; "
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"disabling it for V1 backend.")
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self.enable_chunked_prefill = False
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assert self.enable_chunked_prefill is not None