@tduncan / Nvidia-Optimization-Stack-VLLM / commits / bdfb02674f

[XPU][Kernel] Tune Triton W8A8 block-FP8 GEMM for Intel B70 (#56063)

Signed-off-by: Pawel Manczak <203671809+pmanczak@users.noreply.github.com> Co-authored-by: Pawel Manczak <203671809+pmanczak@users.noreply.github.com>

pmanczak committed Oct 2, 2026 at 13:56 UTC bdfb02674fc0eaa2b9023420b02a8d4e23a69957
27 files changed +2174 -9
benchmarks/kernels/benchmark_w8a8_block_fp8.py
+42 -9
@@ -23,9 +23,11 @@ from vllm.utils.platform_utils import get_device_name_as_file_name
23
24 mp.set_start_method("spawn", force=True)
25
26 -assert current_platform.is_cuda() or current_platform.is_rocm(), (
27 - "Only support tune w8a8 block fp8 kernel on CUDA/ROCm device."
28 -)
26 +assert (
27 + current_platform.is_cuda()
28 + or current_platform.is_rocm()
29 + or current_platform.is_xpu()
30 +), "Only support tune w8a8 block fp8 kernel on CUDA/ROCm/XPU device."
31
32 DTYPE_MAP = {
33 "float32": torch.float32,
@@ -138,6 +140,29 @@ def get_configs_compute_bound():
140 return configs
141
142
143 +def get_xpu_tuning_space():
144 + # NOTE: curated subset of get_configs_compute_bound(); the full grid is
145 + # too slow to tune on XPU due to per-config Triton JIT compile time.
146 + configs = []
147 + for num_stages in [2, 3]:
148 + for block_m in [32, 64, 128]:
149 + for block_k in [64, 128]:
150 + for block_n in [128, 256]:
151 + for num_warps in [4, 8, 16, 32]:
152 + for group_size in [1, 32]:
153 + configs.append(
154 + {
155 + "BLOCK_SIZE_M": block_m,
156 + "BLOCK_SIZE_N": block_n,
157 + "BLOCK_SIZE_K": block_k,
158 + "GROUP_SIZE_M": group_size,
159 + "num_warps": num_warps,
160 + "num_stages": num_stages,
161 + }
162 + )
163 + return configs
164 +
165 +
166 def get_weight_shapes(tp_size):
167 # NOTE(HandH1998): The weight shapes only works for DeepSeek-V3.
168 # Modify them, if you tune for another different model.
@@ -208,13 +233,14 @@ def tune(M, N, K, block_size, out_dtype, search_space, input_type):
233 fp8_info = torch.finfo(torch.float8_e4m3fn)
234 fp8_max, fp8_min = fp8_info.max, fp8_info.min
235
236 + device = current_platform.device_type
237 A_fp32 = (
212 - (torch.rand(M, K, dtype=torch.float32, device="cuda") - 0.5) * 2 * fp8_max
238 + (torch.rand(M, K, dtype=torch.float32, device=device) - 0.5) * 2 * fp8_max
239 )
240 A = A_fp32.clamp(min=fp8_min, max=fp8_max).to(torch.float8_e4m3fn)
241
242 B_fp32 = (
217 - (torch.rand(N, K, dtype=torch.float32, device="cuda") - 0.5) * 2 * fp8_max
243 + (torch.rand(N, K, dtype=torch.float32, device=device) - 0.5) * 2 * fp8_max
244 )
245 B = B_fp32.clamp(min=fp8_min, max=fp8_max).to(torch.float8_e4m3fn)
246 else:
@@ -224,9 +250,9 @@ def tune(M, N, K, block_size, out_dtype, search_space, input_type):
250 n_tiles = (N + block_n - 1) // block_n
251 k_tiles = (K + block_k - 1) // block_k
252
227 - As = torch.rand(M, k_tiles, dtype=torch.float32, device="cuda") * factor_for_scale
253 + As = torch.rand(M, k_tiles, dtype=torch.float32, device=device) * factor_for_scale
254 Bs = (
229 - torch.rand(n_tiles, k_tiles, dtype=torch.float32, device="cuda")
255 + torch.rand(n_tiles, k_tiles, dtype=torch.float32, device=device)
256 * factor_for_scale
257 )
258
@@ -297,7 +323,11 @@ def tune_on_gpu(args_dict):
323 save_path = args.save_path
324 input_type = args.input_type
325
300 - search_space = get_configs_compute_bound()
326 + search_space = (
327 + get_xpu_tuning_space()
328 + if current_platform.is_xpu()
329 + else get_configs_compute_bound()
330 + )
331 search_space = [
332 config for config in search_space if block_k % config["BLOCK_SIZE_K"] == 0
333 ]
@@ -342,7 +372,10 @@ def main(args):
372 raise RuntimeError("No GPU available for tuning")
373 print(f"Found {num_gpus} GPUs for parallel tuning")
374
345 - torch.cuda.init()
375 + if current_platform.is_xpu():
376 + torch.xpu.init()
377 + else:
378 + torch.cuda.init()
379
380 if args.batch_size is None:
381 batch_sizes = [
vllm/model_executor/layers/quantization/utils/configs/N=1536,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 128,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 16,
8 + "num_stages": 2
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 1,
15 + "num_warps": 32,
16 + "num_stages": 2
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 1,
23 + "num_warps": 32,
24 + "num_stages": 2
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 2
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 32,
40 + "num_stages": 3
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 32,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 32,
48 + "num_stages": 2
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 64,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 1,
55 + "num_warps": 32,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 128,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 1,
63 + "num_warps": 32,
64 + "num_stages": 3
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 64,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 1,
71 + "num_warps": 16,
72 + "num_stages": 3
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 1,
79 + "num_warps": 16,
80 + "num_stages": 3
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=2048,K=11008,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 128,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 32,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 1,
15 + "num_warps": 32,
16 + "num_stages": 2
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 1,
23 + "num_warps": 32,
24 + "num_stages": 3
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 2
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 32,
40 + "num_stages": 3
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 32,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 32,
48 + "num_stages": 3
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 64,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 1,
55 + "num_warps": 16,
56 + "num_stages": 2
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 64,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 1,
63 + "num_warps": 16,
64 + "num_stages": 3
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 64,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 1,
71 + "num_warps": 16,
72 + "num_stages": 3
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 1,
79 + "num_warps": 16,
80 + "num_stages": 2
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=2048,K=2048,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 128,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 32,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 32,
15 + "num_warps": 32,
16 + "num_stages": 3
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 1,
23 + "num_warps": 32,
24 + "num_stages": 2
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 1,
31 + "num_warps": 32,
32 + "num_stages": 2
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 32,
39 + "num_warps": 32,
40 + "num_stages": 2
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 32,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 32,
48 + "num_stages": 2
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 64,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 32,
55 + "num_warps": 16,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 128,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 32,
64 + "num_stages": 2
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 128,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 1,
71 + "num_warps": 32,
72 + "num_stages": 3
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 128,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 1,
79 + "num_warps": 32,
80 + "num_stages": 2
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=2112,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 128,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 32,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 32,
15 + "num_warps": 32,
16 + "num_stages": 2
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 128,
22 + "GROUP_SIZE_M": 32,
23 + "num_warps": 32,
24 + "num_stages": 3
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 1,
31 + "num_warps": 32,
32 + "num_stages": 3
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 32,
39 + "num_warps": 16,
40 + "num_stages": 3
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 32,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 8,
48 + "num_stages": 3
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 128,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 1,
55 + "num_warps": 32,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 32,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 8,
64 + "num_stages": 2
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 32,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 1,
71 + "num_warps": 8,
72 + "num_stages": 2
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 1,
79 + "num_warps": 16,
80 + "num_stages": 2
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=22016,K=2048,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 64,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 16,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 32,
15 + "num_warps": 32,
16 + "num_stages": 2
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 32,
23 + "num_warps": 32,
24 + "num_stages": 2
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 2
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 8,
40 + "num_stages": 2
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 64,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 16,
48 + "num_stages": 2
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 64,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 32,
55 + "num_warps": 16,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 128,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 32,
64 + "num_stages": 3
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 64,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 32,
71 + "num_warps": 16,
72 + "num_stages": 3
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 32,
79 + "num_warps": 16,
80 + "num_stages": 2
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=24576,K=4096,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 64,
6 + "GROUP_SIZE_M": 1,
7 + "num_warps": 16,
8 + "num_stages": 2
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 1,
15 + "num_warps": 32,
16 + "num_stages": 3
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 1,
23 + "num_warps": 32,
24 + "num_stages": 2
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 3
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 8,
40 + "num_stages": 3
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 64,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 16,
48 + "num_stages": 3
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 64,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 32,
55 + "num_warps": 16,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 64,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 16,
64 + "num_stages": 2
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 64,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 32,
71 + "num_warps": 16,
72 + "num_stages": 3
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 32,
79 + "num_warps": 16,
80 + "num_stages": 3
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=24576,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 64,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 16,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 32,
15 + "num_warps": 32,
16 + "num_stages": 3
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 1,
23 + "num_warps": 32,
24 + "num_stages": 3
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 2
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 32,
39 + "num_warps": 8,
40 + "num_stages": 3
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 64,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 16,
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vllm/model_executor/layers/quantization/utils/configs/N=28672,K=4096,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=3072,K=1536,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=3072,K=2048,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=3072,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=32768,K=512,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
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@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=4096,K=12288,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
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@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=4096,K=14336,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=4096,K=4096,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=4096,K=512,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=4608,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=512,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=576,K=2048,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=576,K=7168,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
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@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=6144,K=4096,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=7168,K=16384,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=7168,K=18432,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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vllm/model_executor/layers/quantization/utils/configs/N=7168,K=2048,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
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16 + "num_stages": 2
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 64,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 32,
23 + "num_warps": 16,
24 + "num_stages": 2
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 2
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 8,
40 + "num_stages": 2
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 64,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 16,
48 + "num_stages": 2
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 128,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 32,
55 + "num_warps": 32,
56 + "num_stages": 2
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 128,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 32,
64 + "num_stages": 2
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 64,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 1,
71 + "num_warps": 16,
72 + "num_stages": 3
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 1,
79 + "num_warps": 16,
80 + "num_stages": 3
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=7168,K=2304,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 128,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 16,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 32,
15 + "num_warps": 32,
16 + "num_stages": 2
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 128,
21 + "BLOCK_SIZE_K": 128,
22 + "GROUP_SIZE_M": 32,
23 + "num_warps": 32,
24 + "num_stages": 3
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 1,
31 + "num_warps": 32,
32 + "num_stages": 3
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 8,
40 + "num_stages": 2
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 64,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 1,
47 + "num_warps": 16,
48 + "num_stages": 3
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 128,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 32,
55 + "num_warps": 32,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 128,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 32,
64 + "num_stages": 2
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 64,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 1,
71 + "num_warps": 16,
72 + "num_stages": 2
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 64,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 1,
79 + "num_warps": 16,
80 + "num_stages": 3
81 + }
82 +}
vllm/model_executor/layers/quantization/utils/configs/N=7168,K=256,device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128].json new
+82
@@ -0,0 +1,82 @@
1 +{
2 + "1": {
3 + "BLOCK_SIZE_M": 32,
4 + "BLOCK_SIZE_N": 128,
5 + "BLOCK_SIZE_K": 64,
6 + "GROUP_SIZE_M": 32,
7 + "num_warps": 16,
8 + "num_stages": 3
9 + },
10 + "4": {
11 + "BLOCK_SIZE_M": 32,
12 + "BLOCK_SIZE_N": 128,
13 + "BLOCK_SIZE_K": 64,
14 + "GROUP_SIZE_M": 32,
15 + "num_warps": 8,
16 + "num_stages": 3
17 + },
18 + "16": {
19 + "BLOCK_SIZE_M": 32,
20 + "BLOCK_SIZE_N": 256,
21 + "BLOCK_SIZE_K": 64,
22 + "GROUP_SIZE_M": 32,
23 + "num_warps": 16,
24 + "num_stages": 2
25 + },
26 + "32": {
27 + "BLOCK_SIZE_M": 32,
28 + "BLOCK_SIZE_N": 128,
29 + "BLOCK_SIZE_K": 64,
30 + "GROUP_SIZE_M": 32,
31 + "num_warps": 32,
32 + "num_stages": 3
33 + },
34 + "64": {
35 + "BLOCK_SIZE_M": 32,
36 + "BLOCK_SIZE_N": 128,
37 + "BLOCK_SIZE_K": 64,
38 + "GROUP_SIZE_M": 1,
39 + "num_warps": 8,
40 + "num_stages": 3
41 + },
42 + "128": {
43 + "BLOCK_SIZE_M": 64,
44 + "BLOCK_SIZE_N": 128,
45 + "BLOCK_SIZE_K": 64,
46 + "GROUP_SIZE_M": 32,
47 + "num_warps": 8,
48 + "num_stages": 2
49 + },
50 + "512": {
51 + "BLOCK_SIZE_M": 128,
52 + "BLOCK_SIZE_N": 128,
53 + "BLOCK_SIZE_K": 64,
54 + "GROUP_SIZE_M": 32,
55 + "num_warps": 8,
56 + "num_stages": 3
57 + },
58 + "1024": {
59 + "BLOCK_SIZE_M": 64,
60 + "BLOCK_SIZE_N": 128,
61 + "BLOCK_SIZE_K": 64,
62 + "GROUP_SIZE_M": 32,
63 + "num_warps": 8,
64 + "num_stages": 3
65 + },
66 + "2048": {
67 + "BLOCK_SIZE_M": 128,
68 + "BLOCK_SIZE_N": 128,
69 + "BLOCK_SIZE_K": 64,
70 + "GROUP_SIZE_M": 32,
71 + "num_warps": 8,
72 + "num_stages": 2
73 + },
74 + "4096": {
75 + "BLOCK_SIZE_M": 128,
76 + "BLOCK_SIZE_N": 128,
77 + "BLOCK_SIZE_K": 64,
78 + "GROUP_SIZE_M": 32,
79 + "num_warps": 32,
80 + "num_stages": 3
81 + }
82 +}