[ROCm] Auto-enable breakable CUDA graphs for DeepseekV41ForCausalLM (#56349)
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
Markus Hartikainen committed
Sep 12, 2026 at 20:47 UTC
c711f740b7c7540c8c4d7f2c26ff6960b427a4cc
2 files changed
+14
-3
tests/test_config.py
+4
@@ -358,6 +358,10 @@ def test_rocm_keeps_compiled_deepseek_defaults(monkeypatch):
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assert "DeepseekV32ForCausalLM" not in breakable_architectures
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assert "DeepseekV32MTPModel" not in breakable_architectures
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assert "GlmMoeDsaForCausalLM" not in breakable_architectures
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+ # V4.1 cannot torch.compile and the ROCm sparse SWA backend only
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+ # supports uniform-batch CUDA graphs, so it must opt in or the
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+ # default FULL_AND_PIECEWISE serve path cannot start.
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+ assert "DeepseekV41ForCausalLM" in breakable_architectures
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# The carve-out takes effect via the runner-selection property
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# (warning_once args must be hashable for its lru_cache).
vllm/config/vllm.py
+10
-3
@@ -110,10 +110,17 @@ def default_breakable_cudagraph_architectures() -> frozenset[str]:
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from vllm.platforms import current_platform
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if current_platform.is_rocm():
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- # Breakable CUDA graphs currently regress performance on ROCm, so no
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- # architecture opts in by default here. Users can still force it with
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+ # Breakable CUDA graphs currently regress performance on ROCm for
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+ # models that can use torch.compile piecewise graphs instead. Do not
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+ # opt those in by default. Users can still force them with
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# VLLM_USE_BREAKABLE_CUDAGRAPH=1.
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- return frozenset()
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+ #
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+ # DeepseekV41ForCausalLM cannot torch.compile, and the ROCm sparse
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+ # SWA backend only reports AttentionCGSupport.UNIFORM_BATCH. Default
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+ # FULL_AND_PIECEWISE then dies at capture unless breakable CUDA
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+ # graphs are on. Enable this architecture so the published AMD
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+ # recipe can start.
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+ return frozenset({"DeepseekV41ForCausalLM"})
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return DEFAULT_BREAKABLE_CUDAGRAPH_ARCHITECTURES
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