A high-throughput and memory-efficient inference and serving engine for LLMs
Mirrored from https://github.com/tduncan-lum/Nvidia-Optimization-Stack---VLLM.git
Synced Nov 9, 13:33 UTC
[AMD][QWEN3-NEXT] FP8 Tunings (#32042)
Signed-off-by: Lifan Shen <lifans@meta.com>
Lifan Shen committed
Jan 27, 2026 at 01:34 UTC
da8d0c441aadcf30dba787d31746c38e5648b70c
5 files changed
+586
-2
benchmarks/kernels/benchmark_w8a8_block_fp8.py
+2
-2
@@ -22,8 +22,8 @@ from vllm.utils.argparse_utils import FlexibleArgumentParser
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mp.set_start_method("spawn", force=True)
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-assert current_platform.is_cuda(), (
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- "Only support tune w8a8 block fp8 kernel on CUDA device."
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+assert current_platform.is_cuda() or current_platform.is_rocm(), (
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+ "Only support tune w8a8 block fp8 kernel on CUDA/ROCm device."
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)
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DTYPE_MAP = {
vllm/model_executor/layers/quantization/utils/configs/N=1024,K=2048,device_name=AMD_Instinct_MI300X,dtype=fp8_w8a8,block_shape=[128,128].json
new
+146
@@ -0,0 +1,146 @@
1
+{
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+ "1": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "2": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "4": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 5
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+ },
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+ "8": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "16": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 5
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+ },
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+ "24": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "32": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 3
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+ },
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+ "48": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "64": {
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "96": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 5
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+ },
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+ "128": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 4
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+ },
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+ "256": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "512": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "1024": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 128,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "1536": {
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+ "BLOCK_SIZE_M": 64,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "2048": {
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+ "BLOCK_SIZE_M": 64,
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+ "BLOCK_SIZE_N": 128,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 8,
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+ "num_stages": 2
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+ },
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+ "3072": {
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+ "BLOCK_SIZE_M": 64,
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "4096": {
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+ "BLOCK_SIZE_M": 64,
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
145
+ }
146
+}
vllm/model_executor/layers/quantization/utils/configs/N=12288,K=2048,device_name=AMD_Instinct_MI300X,dtype=fp8_w8a8,block_shape=[128,128].json
new
+146
@@ -0,0 +1,146 @@
1
+{
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+ "1": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "2": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "4": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "8": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 3
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+ },
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+ "16": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "24": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "32": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 128,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 8,
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+ "num_stages": 4
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+ },
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+ "48": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "64": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "96": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_N": 128,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "128": {
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+ "BLOCK_SIZE_M": 64,
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+ "BLOCK_SIZE_N": 128,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 8,
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+ "num_stages": 2
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+ },
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+ "256": {
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+ "BLOCK_SIZE_M": 64,
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "512": {
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+ "BLOCK_SIZE_M": 256,
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+ "BLOCK_SIZE_N": 128,
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+ "BLOCK_SIZE_K": 64,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "1024": {
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+ "BLOCK_SIZE_M": 128,
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 64,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "1536": {
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 64,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "2048": {
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+ "BLOCK_SIZE_M": 128,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ },
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+ "3072": {
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+ "BLOCK_SIZE_N": 256,
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+ "num_warps": 4,
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+ },
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+ "4096": {
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
145
+ }
146
+}
vllm/model_executor/layers/quantization/utils/configs/N=2048,K=4096,device_name=AMD_Instinct_MI300X,dtype=fp8_w8a8,block_shape=[128,128].json
new
+146
@@ -0,0 +1,146 @@
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+{
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+ "1": {
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+ "num_stages": 3
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+ },
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+ "2": {
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "4": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_warps": 4,
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+ "num_stages": 3
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+ },
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+ "8": {
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+ },
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+ "16": {
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+ "GROUP_SIZE_M": 16,
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+ },
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+ "num_warps": 4,
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+ "num_stages": 3
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+ },
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+ "32": {
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "48": {
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+ "GROUP_SIZE_M": 64,
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+ },
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+ "64": {
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+ },
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+ "num_warps": 4,
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+ },
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+ "128": {
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ },
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+ "256": {
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+ "BLOCK_SIZE_M": 16,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "512": {
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 1,
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+ "num_warps": 4,
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+ },
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+ "1024": {
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+ },
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "2048": {
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "3072": {
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
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+ },
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+ "4096": {
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+ "BLOCK_SIZE_M": 128,
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+ "BLOCK_SIZE_N": 256,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "num_stages": 2
145
+ }
146
+}
vllm/model_executor/layers/quantization/utils/configs/N=9216,K=2048,device_name=AMD_Instinct_MI300X,dtype=fp8_w8a8,block_shape=[128,128].json
new
+146
@@ -0,0 +1,146 @@
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+{
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+ "1": {
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 16,
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+ "num_stages": 2
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+ },
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+ "2": {
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+ "BLOCK_SIZE_N": 64,
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+ "BLOCK_SIZE_K": 128,
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+ "GROUP_SIZE_M": 64,
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+ "num_warps": 4,
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+ "num_stages": 4
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+ },
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+ "4": {
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+ "BLOCK_SIZE_K": 128,
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+ "num_warps": 4,
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+ "num_stages": 3
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+ },
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+ "8": {
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+ },
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+ "16": {
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+ },
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+ "512": {
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+ "GROUP_SIZE_M": 32,
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+ "num_warps": 4,
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+ "1024": {
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+ "BLOCK_SIZE_K": 128,
142
+ "GROUP_SIZE_M": 32,
143
+ "num_warps": 4,
144
+ "num_stages": 2
145
+ }
146
+}