[CI][NIXL] Fix flaky DP+EP test port conflict (#50171)
Signed-off-by: Divakar Verma <divakar.verma@amd.com>
Divakar Verma committed
Jul 28, 2026 at 20:12 UTC
fe65aa6a97981c815800daa4bf49d8356b8c4988
1 file changed
+4
-1
tests/v1/kv_connector/nixl_integration/run_accuracy_test.sh
+4
-1
@@ -227,9 +227,12 @@ run_tests_for_model() {
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# Calculate side channel port
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SIDE_CHANNEL_PORT=$((5659 + i * $DECODER_TP_SIZE))
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INTERNAL_PORT=$((DECODER_INTERNAL_PORT_BASE + i * INTERNAL_PORT_STRIDE))
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- DECODER_INTERNAL_PORT_ENV=
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+ # For non-DP mode, set VLLM_PORT to pin the internal port;
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+ # For DP mode, set VLLM_DP_MASTER_PORT instead to avoid race condition.
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if [[ -z "${DP_EP:-}" ]]; then
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DECODER_INTERNAL_PORT_ENV="VLLM_PORT=$INTERNAL_PORT"
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+ else
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+ DECODER_INTERNAL_PORT_ENV="VLLM_DP_MASTER_PORT=$INTERNAL_PORT"
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fi
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echo "Starting decode instance $i on GPU $GPU_ID, port $PORT"