| 1 | /* |
| 2 | * emulator main execution loop |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/qemu-print.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "qapi/type-helpers.h" |
| 24 | #include "hw/core/cpu.h" |
| 25 | #include "accel/tcg/cpu-loop.h" |
| 26 | #include "accel/tcg/cpu-ops.h" |
| 27 | #include "accel/tcg/helper-retaddr.h" |
| 28 | #include "trace.h" |
| 29 | #include "disas/disas.h" |
| 30 | #include "exec/cpu-interrupt.h" |
| 31 | #include "exec/page-protection.h" |
| 32 | #include "exec/mmap-lock.h" |
| 33 | #include "exec/translation-block.h" |
| 34 | #include "tcg/tcg.h" |
| 35 | #include "qemu/atomic.h" |
| 36 | #include "qemu/rcu.h" |
| 37 | #include "exec/log.h" |
| 38 | #include "qemu/main-loop.h" |
| 39 | #include "exec/icount.h" |
| 40 | #include "exec/replay-core.h" |
| 41 | #include "system/tcg.h" |
| 42 | #include "exec/helper-proto-common.h" |
| 43 | #include "tcg-accel-ops.h" |
| 44 | #include "tb-jmp-cache.h" |
| 45 | #include "tb-hash.h" |
| 46 | #include "tb-context.h" |
| 47 | #include "tb-internal.h" |
| 48 | #include "internal-common.h" |
| 49 | #if !defined(CONFIG_USER_ONLY) |
| 50 | #include "accel/tcg/iommu.h" |
| 51 | #endif |
| 52 | |
| 53 | /* -icount align implementation. */ |
| 54 | |
| 55 | typedef struct SyncClocks { |
| 56 | int64_t diff_clk; |
| 57 | int64_t last_cpu_icount; |
| 58 | int64_t realtime_clock; |
| 59 | } SyncClocks; |
| 60 | |
| 61 | #if !defined(CONFIG_USER_ONLY) |
| 62 | /* Allow the guest to have a max 3ms advance. |
| 63 | * The difference between the 2 clocks could therefore |
| 64 | * oscillate around 0. |
| 65 | */ |
| 66 | #define VM_CLOCK_ADVANCE 3000000 |
| 67 | #define THRESHOLD_REDUCE 1.5 |
| 68 | #define MAX_DELAY_PRINT_RATE 2000000000LL |
| 69 | #define MAX_NB_PRINTS 100 |
| 70 | |
| 71 | int64_t max_delay; |
| 72 | int64_t max_advance; |
| 73 | |
| 74 | static void align_clocks(SyncClocks *sc, CPUState *cpu) |
| 75 | { |
| 76 | int64_t cpu_icount; |
| 77 | |
| 78 | if (!icount_align_option) { |
| 79 | return; |
| 80 | } |
| 81 | |
| 82 | cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low; |
| 83 | sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount); |
| 84 | sc->last_cpu_icount = cpu_icount; |
| 85 | |
| 86 | if (sc->diff_clk > VM_CLOCK_ADVANCE) { |
| 87 | #ifndef _WIN32 |
| 88 | struct timespec sleep_delay, rem_delay; |
| 89 | sleep_delay.tv_sec = sc->diff_clk / 1000000000LL; |
| 90 | sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL; |
| 91 | if (nanosleep(&sleep_delay, &rem_delay) < 0) { |
| 92 | sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec; |
| 93 | } else { |
| 94 | sc->diff_clk = 0; |
| 95 | } |
| 96 | #else |
| 97 | Sleep(sc->diff_clk / SCALE_MS); |
| 98 | sc->diff_clk = 0; |
| 99 | #endif |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | static void print_delay(const SyncClocks *sc) |
| 104 | { |
| 105 | static float threshold_delay; |
| 106 | static int64_t last_realtime_clock; |
| 107 | static int nb_prints; |
| 108 | |
| 109 | if (icount_align_option && |
| 110 | sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE && |
| 111 | nb_prints < MAX_NB_PRINTS) { |
| 112 | if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) || |
| 113 | (-sc->diff_clk / (float)1000000000LL < |
| 114 | (threshold_delay - THRESHOLD_REDUCE))) { |
| 115 | threshold_delay = (-sc->diff_clk / 1000000000LL) + 1; |
| 116 | qemu_printf("Warning: The guest is now late by %.1f to %.1f seconds\n", |
| 117 | threshold_delay - 1, |
| 118 | threshold_delay); |
| 119 | nb_prints++; |
| 120 | last_realtime_clock = sc->realtime_clock; |
| 121 | } |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | static void init_delay_params(SyncClocks *sc, CPUState *cpu) |
| 126 | { |
| 127 | if (!icount_align_option) { |
| 128 | return; |
| 129 | } |
| 130 | sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); |
| 131 | sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; |
| 132 | sc->last_cpu_icount |
| 133 | = cpu->icount_extra + cpu->neg.icount_decr.u16.low; |
| 134 | if (sc->diff_clk < max_delay) { |
| 135 | max_delay = sc->diff_clk; |
| 136 | } |
| 137 | if (sc->diff_clk > max_advance) { |
| 138 | max_advance = sc->diff_clk; |
| 139 | } |
| 140 | |
| 141 | /* Print every 2s max if the guest is late. We limit the number |
| 142 | of printed messages to NB_PRINT_MAX(currently 100) */ |
| 143 | print_delay(sc); |
| 144 | } |
| 145 | #else |
| 146 | static void align_clocks(SyncClocks *sc, const CPUState *cpu) |
| 147 | { |
| 148 | } |
| 149 | |
| 150 | static void init_delay_params(SyncClocks *sc, const CPUState *cpu) |
| 151 | { |
| 152 | } |
| 153 | #endif /* CONFIG USER ONLY */ |
| 154 | |
| 155 | struct tb_desc { |
| 156 | TCGTBCPUState s; |
| 157 | CPUArchState *env; |
| 158 | tb_page_addr_t page_addr0; |
| 159 | }; |
| 160 | |
| 161 | static bool tb_lookup_cmp(const void *p, const void *d) |
| 162 | { |
| 163 | const TranslationBlock *tb = p; |
| 164 | const struct tb_desc *desc = d; |
| 165 | |
| 166 | if ((tb_cflags(tb) & CF_PCREL || tb->pc == desc->s.pc) && |
| 167 | tb_page_addr0(tb) == desc->page_addr0 && |
| 168 | tb->cs_base == desc->s.cs_base && |
| 169 | tb->flags == desc->s.flags && |
| 170 | tb_cflags(tb) == desc->s.cflags) { |
| 171 | /* check next page if needed */ |
| 172 | tb_page_addr_t tb_phys_page1 = tb_page_addr1(tb); |
| 173 | if (tb_phys_page1 == -1) { |
| 174 | return true; |
| 175 | } else { |
| 176 | tb_page_addr_t phys_page1; |
| 177 | vaddr virt_page1; |
| 178 | |
| 179 | /* |
| 180 | * We know that the first page matched, and an otherwise valid TB |
| 181 | * encountered an incomplete instruction at the end of that page, |
| 182 | * therefore we know that generating a new TB from the current PC |
| 183 | * must also require reading from the next page -- even if the |
| 184 | * second pages do not match, and therefore the resulting insn |
| 185 | * is different for the new TB. Therefore any exception raised |
| 186 | * here by the faulting lookup is not premature. |
| 187 | */ |
| 188 | virt_page1 = TARGET_PAGE_ALIGN(desc->s.pc); |
| 189 | phys_page1 = get_page_addr_code(desc->env, virt_page1); |
| 190 | if (tb_phys_page1 == phys_page1) { |
| 191 | return true; |
| 192 | } |
| 193 | } |
| 194 | } |
| 195 | return false; |
| 196 | } |
| 197 | |
| 198 | static TranslationBlock *tb_htable_lookup(CPUState *cpu, TCGTBCPUState s) |
| 199 | { |
| 200 | tb_page_addr_t phys_pc; |
| 201 | struct tb_desc desc; |
| 202 | uint32_t h; |
| 203 | |
| 204 | desc.s = s; |
| 205 | desc.env = cpu_env(cpu); |
| 206 | phys_pc = get_page_addr_code(desc.env, s.pc); |
| 207 | if (phys_pc == -1) { |
| 208 | return NULL; |
| 209 | } |
| 210 | desc.page_addr0 = phys_pc; |
| 211 | h = tb_hash_func(phys_pc, (s.cflags & CF_PCREL ? 0 : s.pc), |
| 212 | s.flags, s.cs_base, s.cflags); |
| 213 | return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); |
| 214 | } |
| 215 | |
| 216 | /** |
| 217 | * tb_lookup: |
| 218 | * @cpu: CPU that will execute the returned translation block |
| 219 | * @pc: guest PC |
| 220 | * @cs_base: arch-specific value associated with translation block |
| 221 | * @flags: arch-specific translation block flags |
| 222 | * @cflags: CF_* flags |
| 223 | * |
| 224 | * Look up a translation block inside the QHT using @pc, @cs_base, @flags and |
| 225 | * @cflags. Uses @cpu's tb_jmp_cache. Might cause an exception, so have a |
| 226 | * longjmp destination ready. |
| 227 | * |
| 228 | * Returns: an existing translation block or NULL. |
| 229 | */ |
| 230 | static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) |
| 231 | { |
| 232 | TranslationBlock *tb; |
| 233 | CPUJumpCache *jc; |
| 234 | uint32_t hash; |
| 235 | |
| 236 | /* we should never be trying to look up an INVALID tb */ |
| 237 | tcg_debug_assert(!(s.cflags & CF_INVALID)); |
| 238 | |
| 239 | hash = tb_jmp_cache_hash_func(s.pc); |
| 240 | jc = cpu->tb_jmp_cache; |
| 241 | |
| 242 | tb = qatomic_read(&jc->array[hash].tb); |
| 243 | if (likely(tb && |
| 244 | jc->array[hash].pc == s.pc && |
| 245 | tb->cs_base == s.cs_base && |
| 246 | tb->flags == s.flags && |
| 247 | tb_cflags(tb) == s.cflags)) { |
| 248 | goto hit; |
| 249 | } |
| 250 | |
| 251 | tb = tb_htable_lookup(cpu, s); |
| 252 | if (tb == NULL) { |
| 253 | return NULL; |
| 254 | } |
| 255 | |
| 256 | jc->array[hash].pc = s.pc; |
| 257 | qatomic_set(&jc->array[hash].tb, tb); |
| 258 | |
| 259 | hit: |
| 260 | /* |
| 261 | * As long as tb is not NULL, the contents are consistent. Therefore, |
| 262 | * the virtual PC has to match for non-CF_PCREL translations. |
| 263 | */ |
| 264 | assert((tb_cflags(tb) & CF_PCREL) || tb->pc == s.pc); |
| 265 | return tb; |
| 266 | } |
| 267 | |
| 268 | static void log_cpu_exec(vaddr pc, CPUState *cpu, |
| 269 | const TranslationBlock *tb) |
| 270 | { |
| 271 | if (qemu_log_in_addr_range(pc)) { |
| 272 | qemu_log_mask(CPU_LOG_EXEC, |
| 273 | "Trace %d: %p [%08" PRIx64 |
| 274 | "/%016" VADDR_PRIx "/%08x/%08x] %s\n", |
| 275 | cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, |
| 276 | tb->flags, tb->cflags, lookup_symbol(pc)); |
| 277 | |
| 278 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
| 279 | FILE *logfile = qemu_log_trylock(); |
| 280 | if (logfile) { |
| 281 | int flags = CPU_DUMP_CCOP; |
| 282 | |
| 283 | if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { |
| 284 | flags |= CPU_DUMP_FPU; |
| 285 | } |
| 286 | if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) { |
| 287 | flags |= CPU_DUMP_VPU; |
| 288 | } |
| 289 | cpu_dump_state(cpu, logfile, flags); |
| 290 | qemu_log_unlock(logfile); |
| 291 | } |
| 292 | } |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc, |
| 297 | uint32_t *cflags) |
| 298 | { |
| 299 | CPUBreakpoint *bp; |
| 300 | bool match_page = false; |
| 301 | |
| 302 | /* |
| 303 | * Singlestep overrides breakpoints. |
| 304 | * This requirement is visible in the record-replay tests, where |
| 305 | * we would fail to make forward progress in reverse-continue. |
| 306 | * |
| 307 | * TODO: gdb singlestep should only override gdb breakpoints, |
| 308 | * so that one could (gdb) singlestep into the guest kernel's |
| 309 | * architectural breakpoint handler. |
| 310 | */ |
| 311 | if (cpu_single_stepping(cpu)) { |
| 312 | return false; |
| 313 | } |
| 314 | |
| 315 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
| 316 | /* |
| 317 | * If we have an exact pc match, trigger the breakpoint. |
| 318 | * Otherwise, note matches within the page. |
| 319 | */ |
| 320 | if (pc == bp->pc) { |
| 321 | bool match_bp = false; |
| 322 | |
| 323 | if (bp->flags & BP_GDB) { |
| 324 | match_bp = true; |
| 325 | } else if (bp->flags & BP_CPU) { |
| 326 | #ifdef CONFIG_USER_ONLY |
| 327 | g_assert_not_reached(); |
| 328 | #else |
| 329 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 330 | assert(tcg_ops->debug_check_breakpoint); |
| 331 | match_bp = tcg_ops->debug_check_breakpoint(cpu); |
| 332 | #endif |
| 333 | } |
| 334 | |
| 335 | if (match_bp) { |
| 336 | cpu->exception_index = EXCP_DEBUG; |
| 337 | return true; |
| 338 | } |
| 339 | } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) == 0) { |
| 340 | match_page = true; |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | /* |
| 345 | * Within the same page as a breakpoint, single-step, |
| 346 | * returning to helper_lookup_tb_ptr after each insn looking |
| 347 | * for the actual breakpoint. |
| 348 | * |
| 349 | * TODO: Perhaps better to record all of the TBs associated |
| 350 | * with a given virtual page that contains a breakpoint, and |
| 351 | * then invalidate them when a new overlapping breakpoint is |
| 352 | * set on the page. Non-overlapping TBs would not be |
| 353 | * invalidated, nor would any TB need to be invalidated as |
| 354 | * breakpoints are removed. |
| 355 | */ |
| 356 | if (match_page) { |
| 357 | *cflags = (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | CF_BP_PAGE | 1; |
| 358 | } |
| 359 | return false; |
| 360 | } |
| 361 | |
| 362 | static inline bool check_for_breakpoints(CPUState *cpu, vaddr pc, |
| 363 | uint32_t *cflags) |
| 364 | { |
| 365 | return unlikely(!QTAILQ_EMPTY(&cpu->breakpoints)) && |
| 366 | check_for_breakpoints_slow(cpu, pc, cflags); |
| 367 | } |
| 368 | |
| 369 | /** |
| 370 | * helper_lookup_tb_ptr: quick check for next tb |
| 371 | * @env: current cpu state |
| 372 | * |
| 373 | * Look for an existing TB matching the current cpu state. |
| 374 | * If found, return the code pointer. If not found, return |
| 375 | * the tcg epilogue so that we return into cpu_tb_exec. |
| 376 | */ |
| 377 | const void *HELPER(lookup_tb_ptr)(CPUArchState *env) |
| 378 | { |
| 379 | CPUState *cpu = env_cpu(env); |
| 380 | TranslationBlock *tb; |
| 381 | |
| 382 | /* |
| 383 | * By definition we've just finished a TB, so I/O is OK. |
| 384 | * Avoid the possibility of calling cpu_io_recompile() if |
| 385 | * a page table walk triggered by tb_lookup() calling |
| 386 | * probe_access_internal() happens to touch an MMIO device. |
| 387 | * The next TB, if we chain to it, will clear the flag again. |
| 388 | */ |
| 389 | cpu->neg.can_do_io = true; |
| 390 | |
| 391 | TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); |
| 392 | s.cflags = curr_cflags(cpu); |
| 393 | |
| 394 | if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { |
| 395 | cpu_loop_exit(cpu); |
| 396 | } |
| 397 | |
| 398 | tb = tb_lookup(cpu, s); |
| 399 | if (tb == NULL) { |
| 400 | return tcg_code_gen_epilogue; |
| 401 | } |
| 402 | |
| 403 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { |
| 404 | log_cpu_exec(s.pc, cpu, tb); |
| 405 | } |
| 406 | |
| 407 | return tb->tc.ptr; |
| 408 | } |
| 409 | |
| 410 | /* Return the current PC from CPU, which may be cached in TB. */ |
| 411 | static vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) |
| 412 | { |
| 413 | if (tb_cflags(tb) & CF_PCREL) { |
| 414 | return cpu->cc->get_pc(cpu); |
| 415 | } else { |
| 416 | return tb->pc; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | /* Execute a TB, and fix up the CPU state afterwards if necessary */ |
| 421 | /* |
| 422 | * Disable CFI checks. |
| 423 | * TCG creates binary blobs at runtime, with the transformed code. |
| 424 | * A TB is a blob of binary code, created at runtime and called with an |
| 425 | * indirect function call. Since such function did not exist at compile time, |
| 426 | * the CFI runtime has no way to verify its signature and would fail. |
| 427 | * TCG is not considered a security-sensitive part of QEMU so this does not |
| 428 | * affect the impact of CFI in environment with high security requirements |
| 429 | */ |
| 430 | static inline TranslationBlock * QEMU_DISABLE_CFI |
| 431 | cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) |
| 432 | { |
| 433 | uintptr_t ret; |
| 434 | TranslationBlock *last_tb; |
| 435 | const void *tb_ptr = itb->tc.ptr; |
| 436 | |
| 437 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { |
| 438 | log_cpu_exec(log_pc(cpu, itb), cpu, itb); |
| 439 | } |
| 440 | |
| 441 | qemu_thread_jit_execute(); |
| 442 | ret = tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr); |
| 443 | cpu->neg.can_do_io = true; |
| 444 | qemu_plugin_disable_mem_helpers(cpu); |
| 445 | /* |
| 446 | * TODO: Delay swapping back to the read-write region of the TB |
| 447 | * until we actually need to modify the TB. The read-only copy, |
| 448 | * coming from the rx region, shares the same host TLB entry as |
| 449 | * the code that executed the exit_tb opcode that arrived here. |
| 450 | * If we insist on touching both the RX and the RW pages, we |
| 451 | * double the host TLB pressure. |
| 452 | */ |
| 453 | last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK)); |
| 454 | *tb_exit = ret & TB_EXIT_MASK; |
| 455 | |
| 456 | trace_exec_tb_exit(last_tb, *tb_exit); |
| 457 | |
| 458 | if (*tb_exit > TB_EXIT_IDX1) { |
| 459 | /* We didn't start executing this TB (eg because the instruction |
| 460 | * counter hit zero); we must restore the guest PC to the address |
| 461 | * of the start of the TB. |
| 462 | */ |
| 463 | const CPUClass *cc = cpu->cc; |
| 464 | const TCGCPUOps *tcg_ops = cc->tcg_ops; |
| 465 | |
| 466 | if (tcg_ops->synchronize_from_tb) { |
| 467 | tcg_ops->synchronize_from_tb(cpu, last_tb); |
| 468 | } else { |
| 469 | tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL)); |
| 470 | assert(cc->set_pc); |
| 471 | cc->set_pc(cpu, last_tb->pc); |
| 472 | } |
| 473 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
| 474 | vaddr pc = log_pc(cpu, last_tb); |
| 475 | if (qemu_log_in_addr_range(pc)) { |
| 476 | qemu_log("Stopped execution of TB chain before %p [%016" |
| 477 | VADDR_PRIx "] %s\n", |
| 478 | last_tb->tc.ptr, pc, lookup_symbol(pc)); |
| 479 | } |
| 480 | } |
| 481 | } |
| 482 | |
| 483 | /* |
| 484 | * If gdb single-step, and we haven't raised another exception, |
| 485 | * raise a debug exception. Single-step with another exception |
| 486 | * is handled in cpu_handle_exception. |
| 487 | */ |
| 488 | if (unlikely(cpu_single_stepping(cpu)) && cpu->exception_index == -1) { |
| 489 | cpu->exception_index = EXCP_DEBUG; |
| 490 | cpu_loop_exit(cpu); |
| 491 | } |
| 492 | |
| 493 | return last_tb; |
| 494 | } |
| 495 | |
| 496 | |
| 497 | static void cpu_exec_enter(CPUState *cpu) |
| 498 | { |
| 499 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 500 | |
| 501 | if (tcg_ops->cpu_exec_enter) { |
| 502 | tcg_ops->cpu_exec_enter(cpu); |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | static void cpu_exec_exit(CPUState *cpu) |
| 507 | { |
| 508 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 509 | |
| 510 | if (tcg_ops->cpu_exec_exit) { |
| 511 | tcg_ops->cpu_exec_exit(cpu); |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | static void cpu_exec_longjmp_cleanup(CPUState *cpu) |
| 516 | { |
| 517 | /* Non-buggy compilers preserve this; assert the correct value. */ |
| 518 | g_assert(cpu == current_cpu); |
| 519 | |
| 520 | #ifdef CONFIG_USER_ONLY |
| 521 | clear_helper_retaddr(); |
| 522 | if (have_mmap_lock()) { |
| 523 | mmap_unlock(); |
| 524 | } |
| 525 | #else |
| 526 | /* |
| 527 | * For softmmu, a tlb_fill fault during translation will land here, |
| 528 | * and we need to release any page locks held. In system mode we |
| 529 | * have one tcg_ctx per thread, so we know it was this cpu doing |
| 530 | * the translation. |
| 531 | * |
| 532 | * Alternative 1: Install a cleanup to be called via an exception |
| 533 | * handling safe longjmp. It seems plausible that all our hosts |
| 534 | * support such a thing. We'd have to properly register unwind info |
| 535 | * for the JIT for EH, rather that just for GDB. |
| 536 | * |
| 537 | * Alternative 2: Set and restore cpu->jmp_env in tb_gen_code to |
| 538 | * capture the cpu_loop_exit longjmp, perform the cleanup, and |
| 539 | * jump again to arrive here. |
| 540 | */ |
| 541 | if (tcg_ctx->gen_tb) { |
| 542 | tb_unlock_pages(tcg_ctx->gen_tb); |
| 543 | tcg_ctx->gen_tb = NULL; |
| 544 | } |
| 545 | #endif |
| 546 | if (bql_locked()) { |
| 547 | bql_unlock(); |
| 548 | } |
| 549 | assert_no_pages_locked(); |
| 550 | } |
| 551 | |
| 552 | void cpu_exec_step_atomic(CPUState *cpu) |
| 553 | { |
| 554 | TranslationBlock *tb; |
| 555 | int tb_exit; |
| 556 | |
| 557 | if (sigsetjmp(cpu->jmp_env, 0) == 0) { |
| 558 | start_exclusive(); |
| 559 | g_assert(cpu == current_cpu); |
| 560 | g_assert(!cpu->running); |
| 561 | cpu->running = true; |
| 562 | |
| 563 | TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); |
| 564 | s.cflags = curr_cflags(cpu); |
| 565 | |
| 566 | /* Execute in a serial context. */ |
| 567 | s.cflags &= ~CF_PARALLEL; |
| 568 | /* After 1 insn, return and release the exclusive lock. */ |
| 569 | s.cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; |
| 570 | /* |
| 571 | * No need to check_for_breakpoints here. |
| 572 | * We only arrive in cpu_exec_step_atomic after beginning execution |
| 573 | * of an insn that includes an atomic operation we can't handle. |
| 574 | * Any breakpoint for this insn will have been recognized earlier. |
| 575 | */ |
| 576 | |
| 577 | tb = tb_lookup(cpu, s); |
| 578 | if (tb == NULL) { |
| 579 | mmap_lock(); |
| 580 | tb = tb_gen_code(cpu, s); |
| 581 | mmap_unlock(); |
| 582 | } |
| 583 | |
| 584 | cpu_exec_enter(cpu); |
| 585 | /* execute the generated code */ |
| 586 | trace_exec_tb(tb, s.pc); |
| 587 | cpu_tb_exec(cpu, tb, &tb_exit); |
| 588 | cpu_exec_exit(cpu); |
| 589 | } else { |
| 590 | cpu_exec_longjmp_cleanup(cpu); |
| 591 | } |
| 592 | |
| 593 | /* |
| 594 | * As we start the exclusive region before codegen we must still |
| 595 | * be in the region if we longjump out of either the codegen or |
| 596 | * the execution. |
| 597 | */ |
| 598 | g_assert(cpu_in_exclusive_context(cpu)); |
| 599 | cpu->running = false; |
| 600 | end_exclusive(); |
| 601 | } |
| 602 | |
| 603 | void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) |
| 604 | { |
| 605 | /* |
| 606 | * Get the rx view of the structure, from which we find the |
| 607 | * executable code address, and tb_target_set_jmp_target can |
| 608 | * produce a pc-relative displacement to jmp_target_addr[n]. |
| 609 | */ |
| 610 | const TranslationBlock *c_tb = tcg_splitwx_to_rx(tb); |
| 611 | uintptr_t offset = tb->jmp_insn_offset[n]; |
| 612 | uintptr_t jmp_rx = (uintptr_t)tb->tc.ptr + offset; |
| 613 | uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff; |
| 614 | |
| 615 | tb->jmp_target_addr[n] = addr; |
| 616 | tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw); |
| 617 | } |
| 618 | |
| 619 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
| 620 | TranslationBlock *tb_next) |
| 621 | { |
| 622 | uintptr_t old; |
| 623 | |
| 624 | qemu_thread_jit_write(); |
| 625 | assert(n < ARRAY_SIZE(tb->jmp_list_next)); |
| 626 | qemu_spin_lock(&tb_next->jmp_lock); |
| 627 | |
| 628 | /* make sure the destination TB is valid */ |
| 629 | if (tb_next->cflags & CF_INVALID) { |
| 630 | goto out_unlock_next; |
| 631 | } |
| 632 | /* Atomically claim the jump destination slot only if it was NULL */ |
| 633 | old = qatomic_cmpxchg(&tb->jmp_dest[n], (uintptr_t)NULL, |
| 634 | (uintptr_t)tb_next); |
| 635 | if (old) { |
| 636 | goto out_unlock_next; |
| 637 | } |
| 638 | |
| 639 | /* patch the native jump address */ |
| 640 | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); |
| 641 | |
| 642 | /* add in TB jmp list */ |
| 643 | tb->jmp_list_next[n] = tb_next->jmp_list_head; |
| 644 | tb_next->jmp_list_head = (uintptr_t)tb | n; |
| 645 | |
| 646 | qemu_spin_unlock(&tb_next->jmp_lock); |
| 647 | |
| 648 | qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n", |
| 649 | tb->tc.ptr, n, tb_next->tc.ptr); |
| 650 | return; |
| 651 | |
| 652 | out_unlock_next: |
| 653 | qemu_spin_unlock(&tb_next->jmp_lock); |
| 654 | } |
| 655 | |
| 656 | static inline bool cpu_handle_halt(CPUState *cpu) |
| 657 | { |
| 658 | #ifndef CONFIG_USER_ONLY |
| 659 | if (cpu->halted) { |
| 660 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 661 | bool leave_halt = tcg_ops->cpu_exec_halt(cpu); |
| 662 | |
| 663 | if (!leave_halt) { |
| 664 | return true; |
| 665 | } |
| 666 | |
| 667 | cpu->halted = 0; |
| 668 | } |
| 669 | #endif /* !CONFIG_USER_ONLY */ |
| 670 | |
| 671 | return false; |
| 672 | } |
| 673 | |
| 674 | static inline void cpu_handle_debug_exception(CPUState *cpu) |
| 675 | { |
| 676 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 677 | CPUWatchpoint *wp; |
| 678 | |
| 679 | if (!cpu->watchpoint_hit) { |
| 680 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
| 681 | wp->flags &= ~BP_WATCHPOINT_HIT; |
| 682 | } |
| 683 | } |
| 684 | |
| 685 | if (tcg_ops->debug_excp_handler) { |
| 686 | tcg_ops->debug_excp_handler(cpu); |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | static inline bool cpu_handle_exception(CPUState *cpu, int *ret) |
| 691 | { |
| 692 | if (cpu->exception_index < 0) { |
| 693 | #ifndef CONFIG_USER_ONLY |
| 694 | if (replay_has_exception() |
| 695 | && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0) { |
| 696 | /* Execute just one insn to trigger exception pending in the log */ |
| 697 | cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) |
| 698 | | CF_NOIRQ | 1; |
| 699 | } |
| 700 | #endif |
| 701 | return false; |
| 702 | } |
| 703 | |
| 704 | if (cpu->exception_index >= EXCP_INTERRUPT) { |
| 705 | /* exit request from the cpu execution loop */ |
| 706 | *ret = cpu->exception_index; |
| 707 | if (*ret == EXCP_DEBUG) { |
| 708 | cpu_handle_debug_exception(cpu); |
| 709 | } |
| 710 | cpu->exception_index = -1; |
| 711 | return true; |
| 712 | } |
| 713 | |
| 714 | #if defined(CONFIG_USER_ONLY) |
| 715 | /* |
| 716 | * If user mode only, we simulate a fake exception which will be |
| 717 | * handled outside the cpu execution loop. |
| 718 | */ |
| 719 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 720 | if (tcg_ops->fake_user_interrupt) { |
| 721 | tcg_ops->fake_user_interrupt(cpu); |
| 722 | } |
| 723 | *ret = cpu->exception_index; |
| 724 | cpu->exception_index = -1; |
| 725 | return true; |
| 726 | #else |
| 727 | if (replay_exception()) { |
| 728 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 729 | |
| 730 | bql_lock(); |
| 731 | tcg_ops->do_interrupt(cpu); |
| 732 | bql_unlock(); |
| 733 | cpu->exception_index = -1; |
| 734 | |
| 735 | if (unlikely(cpu_single_stepping(cpu))) { |
| 736 | /* |
| 737 | * After processing the exception, ensure an EXCP_DEBUG is |
| 738 | * raised when single-stepping so that GDB doesn't miss the |
| 739 | * next instruction. |
| 740 | */ |
| 741 | *ret = EXCP_DEBUG; |
| 742 | cpu_handle_debug_exception(cpu); |
| 743 | return true; |
| 744 | } |
| 745 | } else if (!replay_has_interrupt()) { |
| 746 | /* give a chance to iothread in replay mode */ |
| 747 | *ret = EXCP_INTERRUPT; |
| 748 | return true; |
| 749 | } |
| 750 | #endif |
| 751 | |
| 752 | return false; |
| 753 | } |
| 754 | |
| 755 | void tcg_kick_vcpu_thread(CPUState *cpu) |
| 756 | { |
| 757 | /* |
| 758 | * Ensure cpu_exec will see the reason why the exit request was set. |
| 759 | * FIXME: this is not always needed. Other accelerators instead |
| 760 | * read interrupt_request and set exit_request on demand from the |
| 761 | * CPU thread; see kvm_arch_pre_run() for example. |
| 762 | */ |
| 763 | qatomic_store_release(&cpu->exit_request, true); |
| 764 | |
| 765 | /* Ensure cpu_exec will see the exit request after TCG has exited. */ |
| 766 | qatomic_store_release(&cpu->neg.icount_decr.u16.high, -1); |
| 767 | } |
| 768 | |
| 769 | static inline bool icount_exit_request(CPUState *cpu) |
| 770 | { |
| 771 | if (!icount_enabled()) { |
| 772 | return false; |
| 773 | } |
| 774 | if (cpu->cflags_next_tb != -1 && !(cpu->cflags_next_tb & CF_USE_ICOUNT)) { |
| 775 | return false; |
| 776 | } |
| 777 | return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0; |
| 778 | } |
| 779 | |
| 780 | static inline bool cpu_handle_interrupt(CPUState *cpu, |
| 781 | TranslationBlock **last_tb) |
| 782 | { |
| 783 | /* |
| 784 | * If we have requested custom cflags with CF_NOIRQ we should |
| 785 | * skip checking here. Any pending interrupts will get picked up |
| 786 | * by the next TB we execute under normal cflags. |
| 787 | */ |
| 788 | if (cpu->cflags_next_tb != -1 && cpu->cflags_next_tb & CF_NOIRQ) { |
| 789 | return false; |
| 790 | } |
| 791 | |
| 792 | /* Clear the interrupt flag now since we're processing |
| 793 | * cpu->interrupt_request and cpu->exit_request. |
| 794 | * Ensure zeroing happens before reading cpu->exit_request or |
| 795 | * cpu->interrupt_request (see also store-release in |
| 796 | * tcg_kick_vcpu_thread()) |
| 797 | */ |
| 798 | qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0); |
| 799 | |
| 800 | #ifdef CONFIG_USER_ONLY |
| 801 | assert(!cpu_test_interrupt(cpu, ~0)); |
| 802 | #else |
| 803 | if (unlikely(cpu_test_interrupt(cpu, ~0))) { |
| 804 | bql_lock(); |
| 805 | if (cpu_test_interrupt(cpu, CPU_INTERRUPT_DEBUG)) { |
| 806 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
| 807 | cpu->exception_index = EXCP_DEBUG; |
| 808 | bql_unlock(); |
| 809 | return true; |
| 810 | } |
| 811 | if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) { |
| 812 | /* Do nothing */ |
| 813 | } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HALT)) { |
| 814 | replay_interrupt(); |
| 815 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); |
| 816 | cpu->halted = 1; |
| 817 | cpu->exception_index = EXCP_HLT; |
| 818 | bql_unlock(); |
| 819 | return true; |
| 820 | } else { |
| 821 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 822 | int interrupt_request = cpu->interrupt_request; |
| 823 | |
| 824 | if (cpu_test_interrupt(cpu, CPU_INTERRUPT_RESET)) { |
| 825 | replay_interrupt(); |
| 826 | tcg_ops->cpu_exec_reset(cpu); |
| 827 | bql_unlock(); |
| 828 | return true; |
| 829 | } |
| 830 | |
| 831 | if (unlikely(cpu->singlestep_flags & SSTEP_NOIRQ)) { |
| 832 | /* Mask out external interrupts for this step. */ |
| 833 | interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; |
| 834 | } |
| 835 | |
| 836 | /* |
| 837 | * The target hook has 3 exit conditions: |
| 838 | * False when the interrupt isn't processed, |
| 839 | * True when it is, and we should restart on a new TB, |
| 840 | * and via longjmp via cpu_loop_exit. |
| 841 | */ |
| 842 | if (tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { |
| 843 | if (!tcg_ops->need_replay_interrupt || |
| 844 | tcg_ops->need_replay_interrupt(interrupt_request)) { |
| 845 | replay_interrupt(); |
| 846 | } |
| 847 | /* |
| 848 | * After processing the interrupt, ensure an EXCP_DEBUG is |
| 849 | * raised when single-stepping so that GDB doesn't miss the |
| 850 | * next instruction. |
| 851 | */ |
| 852 | if (unlikely(cpu_single_stepping(cpu))) { |
| 853 | cpu->exception_index = EXCP_DEBUG; |
| 854 | bql_unlock(); |
| 855 | return true; |
| 856 | } |
| 857 | cpu->exception_index = -1; |
| 858 | *last_tb = NULL; |
| 859 | } |
| 860 | } |
| 861 | if (cpu_test_interrupt(cpu, CPU_INTERRUPT_EXITTB)) { |
| 862 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_EXITTB); |
| 863 | /* ensure that no TB jump will be modified as |
| 864 | the program flow was changed */ |
| 865 | *last_tb = NULL; |
| 866 | } |
| 867 | |
| 868 | /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ |
| 869 | bql_unlock(); |
| 870 | } |
| 871 | #endif /* !CONFIG_USER_ONLY */ |
| 872 | |
| 873 | /* |
| 874 | * Finally, check if we need to exit to the main loop. |
| 875 | * The corresponding store-release is in cpu_exit. |
| 876 | */ |
| 877 | if (unlikely(qatomic_load_acquire(&cpu->exit_request)) || icount_exit_request(cpu)) { |
| 878 | if (cpu->exception_index == -1) { |
| 879 | cpu->exception_index = EXCP_INTERRUPT; |
| 880 | } |
| 881 | return true; |
| 882 | } |
| 883 | |
| 884 | return false; |
| 885 | } |
| 886 | |
| 887 | static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, |
| 888 | vaddr pc, TranslationBlock **last_tb, |
| 889 | int *tb_exit) |
| 890 | { |
| 891 | trace_exec_tb(tb, pc); |
| 892 | tb = cpu_tb_exec(cpu, tb, tb_exit); |
| 893 | if (*tb_exit != TB_EXIT_REQUESTED) { |
| 894 | *last_tb = tb; |
| 895 | return; |
| 896 | } |
| 897 | |
| 898 | *last_tb = NULL; |
| 899 | if (cpu_loop_exit_requested(cpu)) { |
| 900 | /* Something asked us to stop executing chained TBs; just |
| 901 | * continue round the main loop. Whatever requested the exit |
| 902 | * will also have set something else (eg exit_request or |
| 903 | * interrupt_request) which will be handled by |
| 904 | * cpu_handle_interrupt. cpu_handle_interrupt will also |
| 905 | * clear cpu->icount_decr.u16.high. |
| 906 | */ |
| 907 | return; |
| 908 | } |
| 909 | |
| 910 | /* Instruction counter expired. */ |
| 911 | assert(icount_enabled()); |
| 912 | #ifndef CONFIG_USER_ONLY |
| 913 | /* Ensure global icount has gone forward */ |
| 914 | icount_update(cpu); |
| 915 | /* Refill decrementer and continue execution. */ |
| 916 | int32_t insns_left = MIN(0xffff, cpu->icount_budget); |
| 917 | cpu->neg.icount_decr.u16.low = insns_left; |
| 918 | cpu->icount_extra = cpu->icount_budget - insns_left; |
| 919 | |
| 920 | /* |
| 921 | * If the next tb has more instructions than we have left to |
| 922 | * execute we need to ensure we find/generate a TB with exactly |
| 923 | * insns_left instructions in it. |
| 924 | */ |
| 925 | if (insns_left > 0 && insns_left < tb->icount) { |
| 926 | assert(insns_left <= CF_COUNT_MASK); |
| 927 | assert(cpu->icount_extra == 0); |
| 928 | cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; |
| 929 | } |
| 930 | #endif |
| 931 | } |
| 932 | |
| 933 | /* main execution loop */ |
| 934 | |
| 935 | static int __attribute__((noinline)) |
| 936 | cpu_exec_loop(CPUState *cpu, SyncClocks *sc) |
| 937 | { |
| 938 | int ret; |
| 939 | |
| 940 | /* if an exception is pending, we execute it here */ |
| 941 | while (!cpu_handle_exception(cpu, &ret)) { |
| 942 | TranslationBlock *last_tb = NULL; |
| 943 | int tb_exit = 0; |
| 944 | |
| 945 | while (!cpu_handle_interrupt(cpu, &last_tb)) { |
| 946 | TranslationBlock *tb; |
| 947 | TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); |
| 948 | s.cflags = cpu->cflags_next_tb; |
| 949 | |
| 950 | /* |
| 951 | * When requested, use an exact setting for cflags for the next |
| 952 | * execution. This is used for icount, precise smc, and stop- |
| 953 | * after-access watchpoints. Since this request should never |
| 954 | * have CF_INVALID set, -1 is a convenient invalid value that |
| 955 | * does not require tcg headers for cpu_common_reset. |
| 956 | */ |
| 957 | if (s.cflags == -1) { |
| 958 | s.cflags = curr_cflags(cpu); |
| 959 | } else { |
| 960 | cpu->cflags_next_tb = -1; |
| 961 | } |
| 962 | |
| 963 | if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { |
| 964 | break; |
| 965 | } |
| 966 | |
| 967 | tb = tb_lookup(cpu, s); |
| 968 | if (tb == NULL) { |
| 969 | CPUJumpCache *jc; |
| 970 | uint32_t h; |
| 971 | |
| 972 | mmap_lock(); |
| 973 | tb = tb_gen_code(cpu, s); |
| 974 | mmap_unlock(); |
| 975 | |
| 976 | /* |
| 977 | * We add the TB in the virtual pc hash table |
| 978 | * for the fast lookup |
| 979 | */ |
| 980 | h = tb_jmp_cache_hash_func(s.pc); |
| 981 | jc = cpu->tb_jmp_cache; |
| 982 | jc->array[h].pc = s.pc; |
| 983 | qatomic_set(&jc->array[h].tb, tb); |
| 984 | } |
| 985 | |
| 986 | #ifndef CONFIG_USER_ONLY |
| 987 | /* |
| 988 | * We don't take care of direct jumps when address mapping |
| 989 | * changes in system emulation. So it's not safe to make a |
| 990 | * direct jump to a TB spanning two pages because the mapping |
| 991 | * for the second page can change. |
| 992 | */ |
| 993 | if (tb_page_addr1(tb) != -1) { |
| 994 | last_tb = NULL; |
| 995 | } |
| 996 | #endif |
| 997 | /* See if we can patch the calling TB. */ |
| 998 | if (last_tb) { |
| 999 | tb_add_jump(last_tb, tb_exit, tb); |
| 1000 | } |
| 1001 | |
| 1002 | cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit); |
| 1003 | |
| 1004 | /* Try to align the host and virtual clocks |
| 1005 | if the guest is in advance */ |
| 1006 | align_clocks(sc, cpu); |
| 1007 | } |
| 1008 | } |
| 1009 | return ret; |
| 1010 | } |
| 1011 | |
| 1012 | static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc) |
| 1013 | { |
| 1014 | /* Prepare setjmp context for exception handling. */ |
| 1015 | if (unlikely(sigsetjmp(cpu->jmp_env, 0) != 0)) { |
| 1016 | cpu_exec_longjmp_cleanup(cpu); |
| 1017 | } |
| 1018 | |
| 1019 | return cpu_exec_loop(cpu, sc); |
| 1020 | } |
| 1021 | |
| 1022 | int cpu_exec(CPUState *cpu) |
| 1023 | { |
| 1024 | int ret; |
| 1025 | SyncClocks sc = { 0 }; |
| 1026 | |
| 1027 | /* replay_interrupt may need current_cpu */ |
| 1028 | current_cpu = cpu; |
| 1029 | |
| 1030 | if (cpu_handle_halt(cpu)) { |
| 1031 | return EXCP_HALTED; |
| 1032 | } |
| 1033 | |
| 1034 | RCU_READ_LOCK_GUARD(); |
| 1035 | cpu_exec_enter(cpu); |
| 1036 | |
| 1037 | /* |
| 1038 | * Calculate difference between guest clock and host clock. |
| 1039 | * This delay includes the delay of the last cycle, so |
| 1040 | * what we have to do is sleep until it is 0. As for the |
| 1041 | * advance/delay we gain here, we try to fix it next time. |
| 1042 | */ |
| 1043 | init_delay_params(&sc, cpu); |
| 1044 | |
| 1045 | ret = cpu_exec_setjmp(cpu, &sc); |
| 1046 | |
| 1047 | cpu_exec_exit(cpu); |
| 1048 | return ret; |
| 1049 | } |
| 1050 | |
| 1051 | bool tcg_exec_realizefn(CPUState *cpu, Error **errp) |
| 1052 | { |
| 1053 | static bool tcg_target_initialized; |
| 1054 | |
| 1055 | if (!tcg_target_initialized) { |
| 1056 | /* Check mandatory TCGCPUOps handlers */ |
| 1057 | const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; |
| 1058 | #ifndef CONFIG_USER_ONLY |
| 1059 | assert(tcg_ops->cpu_exec_halt); |
| 1060 | assert(tcg_ops->cpu_exec_interrupt); |
| 1061 | assert(tcg_ops->cpu_exec_reset); |
| 1062 | assert(tcg_ops->pointer_wrap); |
| 1063 | #endif /* !CONFIG_USER_ONLY */ |
| 1064 | assert(tcg_ops->translate_code); |
| 1065 | assert(tcg_ops->get_tb_cpu_state); |
| 1066 | assert(tcg_ops->mmu_index); |
| 1067 | tcg_ops->initialize(); |
| 1068 | tcg_target_initialized = true; |
| 1069 | } |
| 1070 | |
| 1071 | cpu->tb_jmp_cache = g_new0(CPUJumpCache, 1); |
| 1072 | tlb_init(cpu); |
| 1073 | #ifndef CONFIG_USER_ONLY |
| 1074 | tcg_iommu_init_notifier_list(cpu); |
| 1075 | #endif /* !CONFIG_USER_ONLY */ |
| 1076 | /* qemu_plugin_vcpu_init_hook delayed until cpu_index assigned. */ |
| 1077 | |
| 1078 | return true; |
| 1079 | } |
| 1080 | |
| 1081 | /* undo the initializations in reverse order */ |
| 1082 | void tcg_exec_unrealizefn(CPUState *cpu) |
| 1083 | { |
| 1084 | #ifndef CONFIG_USER_ONLY |
| 1085 | tcg_iommu_free_notifier_list(cpu); |
| 1086 | #endif /* !CONFIG_USER_ONLY */ |
| 1087 | |
| 1088 | tlb_destroy(cpu); |
| 1089 | g_free_rcu(cpu->tb_jmp_cache, rcu); |
| 1090 | } |