| 1 | /* |
| 2 | * Internal execution defines for qemu (target agnostic) |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * SPDX-License-Identifier: LGPL-2.1-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef ACCEL_TCG_INTERNAL_COMMON_H |
| 10 | #define ACCEL_TCG_INTERNAL_COMMON_H |
| 11 | |
| 12 | #include "exec/cpu-common.h" |
| 13 | #include "exec/translation-block.h" |
| 14 | #include "exec/mmap-lock.h" |
| 15 | #include "accel/tcg/tb-cpu-state.h" |
| 16 | |
| 17 | extern int64_t max_delay; |
| 18 | extern int64_t max_advance; |
| 19 | |
| 20 | extern bool one_insn_per_tb; |
| 21 | |
| 22 | extern bool icount_align_option; |
| 23 | |
| 24 | /* |
| 25 | * Return true if CS is not running in parallel with other cpus, either |
| 26 | * because there are no other cpus or we are within an exclusive context. |
| 27 | */ |
| 28 | static inline bool cpu_in_serial_context(CPUState *cs) |
| 29 | { |
| 30 | return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs); |
| 31 | } |
| 32 | |
| 33 | /** |
| 34 | * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? |
| 35 | * @cs: CPUState pointer |
| 36 | * |
| 37 | * The memory callbacks are installed if a plugin has instrumented an |
| 38 | * instruction for memory. This can be useful to know if you want to |
| 39 | * force a slow path for a series of memory accesses. |
| 40 | */ |
| 41 | static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) |
| 42 | { |
| 43 | #ifdef CONFIG_PLUGIN |
| 44 | return !!cpu->neg.plugin_mem_cbs; |
| 45 | #else |
| 46 | return false; |
| 47 | #endif |
| 48 | } |
| 49 | |
| 50 | TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s); |
| 51 | void page_init(void); |
| 52 | void tb_htable_init(void); |
| 53 | void tb_reset_jump(TranslationBlock *tb, int n); |
| 54 | TranslationBlock *tb_link_page(TranslationBlock *tb); |
| 55 | void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, |
| 56 | uintptr_t host_pc); |
| 57 | |
| 58 | /** |
| 59 | * tlb_init - initialize a CPU's TLB |
| 60 | * @cpu: CPU whose TLB should be initialized |
| 61 | */ |
| 62 | void tlb_init(CPUState *cpu); |
| 63 | /** |
| 64 | * tlb_destroy - destroy a CPU's TLB |
| 65 | * @cpu: CPU whose TLB should be destroyed |
| 66 | */ |
| 67 | void tlb_destroy(CPUState *cpu); |
| 68 | |
| 69 | bool tcg_exec_realizefn(CPUState *cpu, Error **errp); |
| 70 | void tcg_exec_unrealizefn(CPUState *cpu); |
| 71 | |
| 72 | /* current cflags for hashing/comparison */ |
| 73 | uint32_t curr_cflags(CPUState *cpu); |
| 74 | |
| 75 | void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); |
| 76 | |
| 77 | /** |
| 78 | * get_page_addr_code_hostp() |
| 79 | * @env: CPUArchState |
| 80 | * @addr: guest virtual address of guest code |
| 81 | * |
| 82 | * See get_page_addr_code() (full-system version) for documentation on the |
| 83 | * return value. |
| 84 | * |
| 85 | * Sets *@hostp as follows. |
| 86 | * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp |
| 87 | * to the host address where @addr's content is kept. |
| 88 | * |
| 89 | * Note: this function can trigger an exception. |
| 90 | */ |
| 91 | tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, |
| 92 | void **hostp); |
| 93 | |
| 94 | /** |
| 95 | * get_page_addr_code() |
| 96 | * @env: CPUArchState |
| 97 | * @addr: guest virtual address of guest code |
| 98 | * |
| 99 | * If we cannot translate and execute from the entire RAM page, or if |
| 100 | * the region is not backed by RAM, returns -1. Otherwise, returns the |
| 101 | * ram_addr_t corresponding to the guest code at @addr. |
| 102 | * |
| 103 | * Note: this function can trigger an exception. |
| 104 | */ |
| 105 | static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, |
| 106 | vaddr addr) |
| 107 | { |
| 108 | void *discard; |
| 109 | return get_page_addr_code_hostp(env, addr, &discard); |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Access to the various translations structures need to be serialised |
| 114 | * via locks for consistency. In user-mode emulation access to the |
| 115 | * memory related structures are protected with mmap_lock. |
| 116 | * In !user-mode we use per-page locks. |
| 117 | */ |
| 118 | #ifdef CONFIG_USER_ONLY |
| 119 | #define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) |
| 120 | #else |
| 121 | #define assert_memory_lock() |
| 122 | #endif |
| 123 | |
| 124 | #if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG) |
| 125 | void assert_no_pages_locked(void); |
| 126 | #else |
| 127 | static inline void assert_no_pages_locked(void) { } |
| 128 | #endif |
| 129 | |
| 130 | #ifdef CONFIG_USER_ONLY |
| 131 | static inline void page_table_config_init(void) { } |
| 132 | #else |
| 133 | void page_table_config_init(void); |
| 134 | #endif |
| 135 | |
| 136 | #ifndef CONFIG_USER_ONLY |
| 137 | G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); |
| 138 | #endif /* CONFIG_USER_ONLY */ |
| 139 | |
| 140 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); |
| 141 | void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); |
| 142 | |
| 143 | void tcg_get_stats(AccelState *accel, GString *buf); |
| 144 | |
| 145 | #endif |